systemverilog中门类型-1-三态门thress state gates

三态门主要有bufif0/bufif1/notif0/notif1

三态使能门实例声明语法：
gate_instantiation ::= enable_gatetype [drive_strength] [delay3] enable_gate_instance { , enable_gate_instance } ;
enable_gatetype ::= bufif0 | bufif1 | notif0 | notif1
enable_gate_instance ::= [ name_of_instance ] ( output_terminal , input_terminal , enable_terminal )

1.驱动强度规格

An optional drive strength specification shall specify the strength of the logic values on the output terminals of the gate instance.

The drive strength specification for a gate instance, with the exception of pullup and pulldown, shall have a strength1 specification and a strength0 specification.
The strength1 specification shall specify the strength of signals with a logic value 1, and the strength0 specification shall specify the strength of signals with a logic value 0.

The strength1 specification shall be one of the following keywords:
supply1 strong1 pull1 weak1
The strength0 specification shall be one of the following keywords:
supply0 strong0 pull0 weak0

Specifying highz1 as strength1 shall cause the gate or switch to output a logic value z in place of a 1.
Specifying highz0 shall cause the gate to output a logic value z in place of a 0.
The strength specifications (highz0, highz1) and (highz1, highz0) shall be considered invalid.
In the absence of a strength specification, the instances shall have the default strengths strong1 and strong0.

2.延迟规格

An optional delay specification shall specify the propagation delay through the gates and switches in a
declaration.
Gates and switches in declarations with no delay specification shall have no propagation delay.
A delay specification can contain up to three delay values, depending on the gate type.
The pullup and pulldown instance declarations shall not include delay specifications.

3.三态逻辑门真值表

实例bufif1的声明：
bufif1 bf1 (outw, inw, controlw);

The delay specification shall be zero, one, two, or three delays.
1.If the delay specification contains three delays, the first delay shall determine the rise delay, the second delay shall determine the fall delay, the third delay shall determine the delay of transitions to z, and the smallest of the three delays shall determine the delay of transitions to x.
2.If the specification contains two delays, the first delay shall determine the output rise delay, the second delay shall determine the output fall delay, and the smaller of the two delays shall apply to output transitions to x and z.
3.If only one delay is specified, it shall specify the delay for all output transitions.
4.If there is no delay specification, there shall be no propagation delay through the gate.