Altera quartus II遇到的问题

编译时提示：

Warning (13024): Output pins are stuck at VCC or GND
　　Warning (13410): Pin "SCLK" is stuck at GND
　　Warning (13410): Pin "SYNCn" is stuck at VCC
　　Warning (13410): Pin "Dout" is stuck at GND

三个输出端都被固定了在GND或者VCC，程序的本意并非如此，分析了一下部分底层模块代码：

always@(negedge CLK or negedge RSTn)
	begin
		if(!RSTn)
			begin
				SCLK <= 1'b0;
			end
		else
			begin
				SCLK <= ~SCLK;
			end
	end
	
	always@(posedge CLK or negedge RSTn)
	begin
		if(!RSTn)
			begin
				counter <= 8'd0;
			end
		else
			begin
				counter <= counter + 1'b1;
				if(counter == 8'd62)
					counter <= 8'd0;
			end
	end

　并没有发现错误，转而分析顶层

module MyDemo(
    input CLK,
    output  SCLK,
    output  SYNCn,
    output  Dout
    );
    wire BUSY;
    reg RSTn = 1'b1;
    reg [20:0] counter;
    reg [15:0] V_Data;
    
    DAC8560 U1(.CLK(CLK),.V_Data(V_Data),.RSTn(RSTn),.SCLK(SCLK),.SYNCn(SYNCn),.Dout(Dout),.BUSY(BUSY));
    
    always@(posedge CLK)
    begin
        if(counter == 21'd2000000)
            begin
                if(V_Data < 16'd60000)
                    V_Data <= V_Data + 16'd10000;
                else
                    begin
                        V_Data <= 16'd0;
                    end
            end
        else
            begin
                counter <= counter + 1'b1;
            end
    end
endmodule

发现复位信号由于为了方便调试将RSTn置为1，将RSTn修改为实际引脚输入，编译后问题解决

module MyDemo(
    input CLK,
    output  SCLK,
    output  SYNCn,
    output  Dout,
    input RSTn
    );

发现always所依赖的敏感信号如果为固定电平，很容易出现这种警告，具体原因待查。