Verilog HDL实现奇数次分频

在数字逻辑电路中，经常需要设计分频电路，本文是通过Verilog HDL实现了奇数次分频。

以下是设计程序源代码：

module freq_div(
// Input
clk_50,
rst_n,
// Output
clk_div2,
clk_div5
);

parameter DIVN = 5;

input clk_50; // Clock
input rst_n; // Reset
output clk_div2; // indicates write transfer
output clk_div5; // strobe input

integer div_count1;
integer div_count2;
reg div2;
reg div5p;
reg div5n;

assign clk_div2=div2;
assign clk_div5=div5p|div5n;

always @(posedge clk_50)
begin
if(!rst_n)
begin
div2 <= 1'b0;
div5p <= 1'b0;
div_count1 <= 0;
end
else
begin
div2 <= ~div2;
if(div_count1 == (DIVN-1))
div_count1 <= 0;
else
begin
if((div_count1 == 1)|(div_count1 == ((DIVN+1)/2)))
begin
div_count1 <= div_count1 + 1;
div5p <= ~div5p;
end
else
div_count1 <= div_count1 + 1;
end
end
end

always @(negedge clk_50)
begin
if(!rst_n)
begin
div5n <= 1'b0;
div_count2 <= 0;
end
else
begin
if(div_count2 == (DIVN-1))
div_count2 <= 0;
else
begin
if((div_count2 == 1)|(div_count2 == ((DIVN+1)/2)))
begin
div_count2 <= div_count2 + 1;
div5n <= ~div5n;
end
else
div_count2 <= div_count2 + 1;
end
end
end

endmodule

以下是测试程序源代码：

`timescale 1ns/1ns

module freq_div_tb();

reg clk_50; // Clock
reg rst_n; // Reset
wire clk_div2;
wire clk_div5;

freq_div U0(
.clk_50(clk_50),
.rst_n(rst_n),
.clk_div2(clk_div2),
.clk_div5(clk_div5)
);

initial
begin
clk_50 = 0;
rst_n = 0;
#10 rst_n = 1;
end

always #2 clk_50 = ~clk_50;

endmodule

以下是modelsim仿真结果：