VCS 仿真脚本makefile样例

详细的参数介绍参考下面的博客

https://www.cnblogs.com/csjt/p/15581396.html

自己的makefile，注意

1 2	SEED = ``date` +%N` `//随机种子的定义取时间` `SIM_COV = -cm line+cond+fsm+tgl+branch` `//代码覆盖率采样的定义`

1 2	`TESTLIST = ahb_mst_burst ahb_mst_single_read32 ahb_mst_single_write32_apb_slv_nrdy \` `ahb_mst_burst_apb_slv_slverr ahb_mst_tight_transfer` `//` `定义测试用例list，将写的测试用例名复制过来并定义为变量 TESTLIST`

vcs:
    vcs +v2k \
    -full64 \
    -sverilog -debug_acc+all  +ntb_random_seed=${SEED} \
    +define+FSDB -fsdb -lca -kdb  +DUMP_VPD ${UVM_HOME}/src/dpi/uvm_dpi.cc -CFLAGS -DVCS -timescale=1ns/1ns  -f filelist.f <br>//VCS 编译命令 这里是编译 还不涉及到运行SIMV二进制文件

1 2	`cov:` `dve -full64 -cov -dir` `./SIMV/*.vdb&` `//运行查看覆盖率`

regress10:
    for((i=1; i<=${number};i++)); do \
        for item in $(TESTLIST); do \
        echo $$item; \
        ./simv  +ntb_random_seed=${SEED} +ntb_solver_array_size_warn=100000 +DUMP_VPD +VPD_FILENAME=./VPD/$${item}_${SEED}.vpd +UVM_TESTNAME=$${item} -l ./LOG/$${item}_${SEED}.log  -cm_dir ./SIMV/$${item}_${SEED}; \
        done; \
    done<br>//使用了两层for循环执行仿真，需要注意的是 执行仿真的时候 需要添加随机种子 将VPD波形文件 VDB覆盖率文件 还有log日志文件 保存到对应的目录下

1 2	`merge:` `urg -full64 -dir` `./SIMV/*.vdb -dbname merged -parallel -report ./SIMV/urgReport<br>//将覆盖率文件merge 生成report`

clean:
    rm -r csrc merged.vdb urgReport  ./LOG/* ./SIMV/* ./VPD/* *.log *.key *.h 
 
generatedir:
    mkdir ./LOG
    mkdir ./SIMV
    mkdir ./VPD

总体的makefile 如下：

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

TOP       = ../tb/rkv_i2c_tb.sv
TEST     ?= rkv_i2c_quick_reg_access_test
VERDI    ?= 0
GUI      ?= 0
COV      ?= 0
SEED      = `date "+%m%d%H%M%S"`
OUT      ?= out
VERB     ?= UVM_HIGH#{UVM_NONE, UVM_LOW, UVM_MEDIUM, UVM_HIGH}
INCDIR   = +incdir+../../rkv_dw_apb_i2c/src \
                     +incdir+../env \
                     +incdir+../agents/{lvc_apb3,lvc_i2c} \
                     +incdir+../{cfg,cov,reg,env,seq_lib} \
                     +incdir+../seq_lib/{.,elem_seqs,user_elem_seqs,user_virt_seqs} \
                     +incdir+../tests/{.,user_tests}
TESTLIST = rkv_i2c_quick_reg_access_test rkv_i2c_master_directed_write_packet_test rkv_i2c_master_directed_interrupt_test \
                rkv_i2c_master_directed_read_packet_test
#rkv_i2c_directed_tx_test rkv_i2c_directed_rx_test
CM = -cm line+cond+fsm+branch+tgl
VCOMP    = vlogan $(INCDIR) -full64 -sverilog -ntb_opts uvm-1.2 -timescale=1ps/1ps -l $(OUT)/log/comp_$(TB_TOP).log  
ELAB     = vcs -full64 -sverilog -ntb_opts uvm-1.2 -debug_all -l $(OUT)/log/elab_$(TB_TOP).log 
RUN      = ./simv +ntb_random_seed=$(SEED) +UVM_NO_RELNOTES +UVM_VERBOSITY=$(VERB) 
COVOPTS  = -full64 -userdata ../docs/testcase.data -plan ../docs/uart_vplan.hvp -elfile ../docs/elfile.el -dir $(OUT)/cov.vdb 
CM_NAME  = $(TEST)_seed_$(SEED)
number = 10
vcs_run= \
    vcs +v2k \
    -full64 \
    -sverilog -debug_acc+all  \
    +define+FSDB -fsdb -lca -kdb  ${UVM_HOME}/src/dpi/uvm_dpi.cc -CFLAGS -DVCS -timescale=1ns/1ns  -f  filelist.f \
    ${CM} +DUMP_VPD -R
ifeq ($(VERDI),1)
    VCOMP  += -kdb
    RUN += -verdi
endif
ifeq ($(GUI),1)
    RUN += -gui
endif
 
ifeq ($(COV),1)
    ELAB  += -cm line+cond+fsm+tgl+branch+assert -cm_dir $(OUT)/cov.vdb
    RUN += -cm line+cond+fsm+tgl+branch+assert -covg_cont_on_error
endif
 
all: clean dcomp comp elab 
#sim_all cov
run_all: clean prepare regsim
vcs:
    vcs +v2k \
    -full64 \
    -sverilog -debug_acc+all  \
    +define+FSDB -fsdb -lca -kdb  ${UVM_HOME}/src/dpi/uvm_dpi.cc -CFLAGS -DVCS -timescale=1ns/1ns  -f  filelist.f \
    ${CM} +DUMP_VPD
simgui:
    ./simv +UVM_TESTNAME=$(TEST) -gui &
 
regsim:
    for((i=1; i<=${number};i++)); do \
        for item in $(TESTLIST); do \
        echo $$item; \
        $(vcs_run) +VPD_FILENAME=$(OUT)/sim/$${item}_seed_$(SEED).vpd +UVM_TESTNAME=$${item} -l $(OUT)/sim/$${item}_seed_$(SEED).log -o $(OUT)/sim/$${item}_seed_$(SEED)simv; \
        done; \
    done
prepare:
    mkdir -p $(OUT)/work
    mkdir -p $(OUT)/log
    mkdir -p $(OUT)/sim
    mkdir -p $(OUT)/obj
    mkdir -p .shadow
    mkdir -p ${OUT}/cov
    mkdir -p ../docs/nd_docs
 
dcomp: prepare
    $(VCOMP)  -f rkv_i2c.flist 
 
 
comp: .shadow/compile_uvm .shadow/compile_lvc_apb .shadow/compile_lvc_i2c
    $(VCOMP)  ../env/rkv_i2c_pkg.sv 
    $(VCOMP)  ../tb/rkv_i2c_if.sv 
    $(VCOMP)  ../tb/rkv_i2c_tb.sv 
 
.shadow/compile_uvm:
    ${VCOMP} -ntb_opts uvm-1.2
    @touch $@;
 
.shadow/compile_lvc_apb:
    $(VCOMP) ../agents/lvc_apb3/lvc_apb_if.sv 
    $(VCOMP) ../agents/lvc_apb3/lvc_apb_pkg.sv 
    #@touch $@;
 
.shadow/compile_lvc_i2c:
    $(VCOMP)  ../agents/lvc_i2c/lvc_i2c_if.sv 
    $(VCOMP)  ../agents/lvc_i2c/lvc_i2c_pkg.sv 
    #@touch $@;
 
elab: comp
    $(ELAB)  $(TOP)
 
run: 
    $(RUN) +UVM_TESTNAME=$(TEST) -l $(OUT)/sim/$(CM_NAME).log -cm_dir $(OUT)/cov -cm_name $(CM_NAME)
 
regr: #$(TESTLIST)
    for t in $(TESTLIST); do \
        $(RUN) +UVM_TESTNAME=$(TESTLIST) -l $(OUT)/sim/$(TESTLIST).log +vpdfile+$(OUT)/sim/$(TESTLIST)_$(SEED)_$(VPDFILE); \
    done
 
editcov:
    urg -format both $(COVOPTS)
    dve $(COVOPTS)
 
viewcov:
    urg -format both $(COVOPTS)
    firefox urgReport/dashboard.html
 
gendoc:
    mono /opt/NaturalDocs/NaturalDocs.exe ../docs/nd_config
   
viewdoc:
    firefox ../docs/nd_docs/index.html &
 
clean:
    -rm -rf csrc DVEfiles ucli.key uvm_dpi.so vc_hdrs.h  *simv* *.vpd *.log *.sml *.fsdb work.* *.vdb
    -rm -rf AN.DB urgReport novas.conf verdiLog vdCovLog novas.rc $(OUT) .shadow
    -rm -rf transcript vsim_stacktrace.vstf vsim.wlf work
    -rm -rf ../docs/nd_docs/*