【Verilog】Gray Code Counter 格雷码计数器
Gray code counters (having one bit change per counter transition) are often used in FIFO design and digital communication.
Here I will show two styles gray code counter.
Style #1
First style gray code counter uses a single set of flip-flops as the Gray code register with accompanying Gray-tobinary conversion, binary increment, and binary-to-Gray conversion.
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Style #2
A second Gray code counter style, the one described below, uses two sets of registers, one a binary counter and a second to capture a binary-to-Gray converted value. The intent of this Gray code counter style #2 is to utilize the binary carry structure, simplify the Gray-to-binary conversion; reduce combinational logic, and increase the upper frequency limit of the Gray code counter.
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Reference:
1.Vijay A. Nebhrajani," Asynchronous FIFO Architectures" part2
2. Clifford E. Cummings, Sunburst Design, Inc " Simulation and Synthesis Techniques for Asynchronous
FIFO Design"
posted on 2009-11-03 11:01 Homography Matrix 阅读(6923) 评论(1) 编辑 收藏 举报