今天在comp.arch.fpga上看到一贴子，是关于FIFO，微光图像处理的项目刚好需要用到这一机制，故，仔细研读之。
bobrics@gmail.com 问道：
Why do you need a FIFO? Is it similar to GBUF, IBUF for clocks to buffer the signals for stability or more like temporary memory?
If it's more like temporary memory, then why not just use intermediate signals to store input signals and delay them (use shift register) a specific number of clocks if needed?
意思是,我们都拿FIFO做什么用?是不是FIFO类似于临时存储器?为什么不用中间信号存储输入信号并使用移位寄存器对其进行特定时钟的延时？
austin <austin@xilinx.com> 答的很好：
FIFOs,
Are useful as a means to synchronize the passing of data between asynchronous clock domains. If you need to communicate both data, and when the data is ready, between two clock domains that are not the same in both frequency and/or phase, a FIFO is a universal means to allow the two clock domains to communicate without error.
To synchonize events in one domain, to another domain requires the use of synchronizing circuits which are notorious in that engineers often get them wrong (they implement ones that do not work). At Intel, there are only a handful of senior engineers who are allowed to do synchronizer circuits.
One of my first ever crisis cases at Xilinx was one where a cutomer had occasional errors in their application, which seemed to come and go at random. They blamed it on different lots of our silicon. Some lots they claimed, were worse, and some were not as bad.
Well, it turned out that the bad lots were slightly slower (but well within specifications), and the good lots (which still had the problem, but not as often) were slightly faster.
The speed difference made a poor FIFO design using CLBs have more (or less) frequent problems. In no case was their FIFO design good. It was always capable of failing, as they spun their own control, without regard to what an incredibly difficult problem it is.
For example, what if the FIFO says it is ready with data to read, when it is not? That leads to a failure. What if it says it is ready to accept data on a write, when it is full? Also, a failure.
Think about your gas gauge saying that you have gas, when you do not: not acceptable.
But, there is a way to design a FIFO to be foolproof, even though in theory, that is impossible (without latency). So, if we do it for you (in hard logic), it saves you from making a very common mistake.
By the way, the secret to low latency synchronization in FIFOs is that the gas gauge could say the tank was empty, when it was not, and then go back to being less than empty without causing any problems (thanks to
Peter for this analogy).
If you used our soft core FIFO (previous to V4), you would also be safe.
But many looked at the FIFO IP, and said to themselves "I am smarter than that -- look at all the wasted logic to do such a simple job!"
Sadly, it is not a simple job. Peter and I were in a 2 day class just last week on just this subject (asynchronous design, and communications between clock domains in large systems). Heck, Peter 'invented' the FIFO back at Fairchild!
Even us "more experinced" engineers realize that we can (must) learn new things.
Since the FIFO is built into the hardware, I imagine it is trivial to instantiate. Let us know if the HDL primitives are in Webpack. It would make no sense to Xilinx not to promote their use, as they prevent engineers from doing things the wrong way, and allow you to pack more into your design, and achieve higher performance.
我的理解：
FIFO是在异步时钟范围内时行同步数据传输的有效方法。当你需要在两个相位与/或频率（都）不同的时钟域内同时对已经准备好的存储块进行读写时，FIFO是一通用的方法，它可实现无误地在两种时钟域下进行数据通讯。
把某一时钟域内的事件同步到另一时钟域内时需要用到同步电路，对此，工程界中已是叫苦连天了，因为工程师们常常在此问题上出错。在Intel，只有熟练的高级工程师才允许使用同步电路。
我在Xilinx工作期间，我所遇到的第一个危机是：我们一个客户的应用出现了偶然性错误，这个问题看上去是随机发生的。他们为此而抱怨我们Xilinx的硅片。他们所要求的大部分都很糟糕，而还是有一些并不是那么坏的。
本文的后面总之是在说，FIFO的设计并非易事。本文作者和Xilinx的同事Heck Peter这些经验丰富的高手也不得说，FIFO绝非易事。不过，如果我们使用成熟的FIFO IP核的话，那将是比较安全的。
