深入基本门电路

http://www.cnblogs.com/yuphone/archive/2010/10/25/1860871.html

1 同步复位的D出发器

module test
(
    input rst_n,
    input clk,
    input d,
    output reg q
);

 always @(posedge clk)
 begin
    if(rst_n)
        q<=1'b0;
    else
        q<=d;
end

endmodule 

2 异步复位的D触发器

module test
(
 input rst_n,
 input clk,
 input d,
 output reg q
);

always @(posedge clk,negedge rst_n)
begin
 if(!rst_n)
  q<=1'b0;
 else
  q<=d;
end

endmodule

3 T触发器

module test
(
 input rst_n,
 input clk,
 input T,
 output reg q
);

always @(posedge clk,negedge rst_n)
begin
 if(!rst_n)
  q<=1'b0;
 else if(T)
  q<= ~q;
end

endmodule

4 JK 触发器

5 RS触发器

 6 存储器

// Listing 4.6
module reg_file
   #(
    parameter B = 8, // number of bits
              W = 2  // number of address bits
   )
   (
    input wire clk,
    input wire wr_en,
    input wire [W-1:0] w_addr, r_addr,
    input wire [B-1:0] w_data,
    output wire [B-1:0] r_data
   );

   // signal declaration
   reg [B-1:0] array_reg [2**W-1:0];

   // body
   // write operation
   always @(posedge clk)
      if (wr_en)
         array_reg[w_addr] <= w_data;
   // read operation
   assign r_data = array_reg[r_addr];

endmodule

7 带时能端的异步复位DFF

// Listing 4.3
module d_ff_en_1seg
   (
    input wire clk, reset,
    input wire en,
    input wire d,
    output reg q
   );

   // body
   always @(posedge clk, posedge reset)
      if (reset)
         q <= 1'b0;
      else if (en)
         q <= d;

endmodule

// Listing 4.4
module d_ff_en_2seg
   (
    input wire clk, reset,
    input wire en,
    input wire d,
    output reg q
   );

   // signal declaration
   reg r_reg, r_next;

   // body
   // D FF
   always @(posedge clk, posedge reset)
      if (reset)
         r_reg <= 1'b0;
      else
         r_reg <= r_next;

   // next-state logic
   always @*
      if (en)
         r_next = d;
      else
         r_next = r_reg;

   // output logic
   always @*
      q = r_reg;

endmodule