(原創) 如何將DE2_70_TV範例加上Sobel Edge Detector? (SOC) (Verilog) (Image Processing) (DE2-70)
本文將DE2-70平台的DE2_70_TV的範例加上Sobel Edge Detector。
Abstract
本文將DE2-70平台的DE2_70_TV的範例加上Sobel Edge Detector。
Introduction
使用環境：Quartus II 8.0 + DE2-70 (Cyclone II EP2C70F896C6N)
DE2_70_TV與DE2_70_D5M_LTM的架構非常類似，都是以SDRAM當做frame buffer，所以若要加上演算法，基本上也是放在SDRAM之前做前處理，或者放在SDRAM之後做後處理。
Sobel Edge Detector解說部分，請參考(原創) 如何實現Real Time的Sobel Edge Detector? (SOC) (Verilog) (Image Processing) (DE2-70) (TRDB-D5M) (TRDB-LTM)與(原創) 如何實現Real Time的Sobel Edge Detector? (SOC) (Verilog) (Image Processing) (DE2) (TRDB-DC2)，本文主要放在如何在DE2_70_TV範例實現。
DE2_70_TV.v / Verilog
1 // --------------------------------------------------------------------
2 // Copyright (c) 2007 by Terasic Technologies Inc.
3 // --------------------------------------------------------------------
4 //
5 // Permission:
6 //
7 // Terasic grants permission to use and modify this code for use
8 // in synthesis for all Terasic Development Boards and Altera Development
9 // Kits made by Terasic. Other use of this code, including the selling
10 // ,duplication, or modification of any portion is strictly prohibited.
11 //
12 // Disclaimer:
13 //
14 // This VHDL/Verilog or C/C++ source code is intended as a design reference
15 // which illustrates how these types of functions can be implemented.
16 // It is the user's responsibility to verify their design for
17 // consistency and functionality through the use of formal
18 // verification methods. Terasic provides no warranty regarding the use
19 // or functionality of this code.
20 //
21 // --------------------------------------------------------------------
22 //
23 // Terasic Technologies Inc
24 // 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
25 // HsinChu County, Taiwan
26 // 302
27 //
28 // web: http://www.terasic.com/
29 // email: support@terasic.com
30 //
31 // --------------------------------------------------------------------
32 //
33 // Major Functions: DE2_70 TV Box
34 //
35 // --------------------------------------------------------------------
36 //
37 // Revision History :
38 // --------------------------------------------------------------------
39 // Ver :| Author :| Mod. Date :| Changes Made:
40 // V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
41 // --------------------------------------------------------------------
42
43 module DE2_70_TV
44 (
45 //////////////////// Clock Input ////////////////////
46 iCLK_28, // 28.63636 MHz
47 iCLK_50, // 50 MHz
48 iCLK_50_2, // 50 MHz
49 iCLK_50_3, // 50 MHz
50 iCLK_50_4, // 50 MHz
51 iEXT_CLOCK, // External Clock
52 //////////////////// Push Button ////////////////////
53 iKEY, // Pushbutton[3:0]
54 //////////////////// DPDT Switch ////////////////////
55 iSW, // Toggle Switch[17:0]
56 //////////////////// 7-SEG Dispaly ////////////////////
57 oHEX0_D, // Seven Segment Digit 0
58 oHEX0_DP, // Seven Segment Digit 0 decimal point
59 oHEX1_D, // Seven Segment Digit 1
60 oHEX1_DP, // Seven Segment Digit 1 decimal point
61 oHEX2_D, // Seven Segment Digit 2
62 oHEX2_DP, // Seven Segment Digit 2 decimal point
63 oHEX3_D, // Seven Segment Digit 3
64 oHEX3_DP, // Seven Segment Digit 3 decimal point
65 oHEX4_D, // Seven Segment Digit 4
66 oHEX4_DP, // Seven Segment Digit 4 decimal point
67 oHEX5_D, // Seven Segment Digit 5
68 oHEX5_DP, // Seven Segment Digit 5 decimal point
69 oHEX6_D, // Seven Segment Digit 6
70 oHEX6_DP, // Seven Segment Digit 6 decimal point
71 oHEX7_D, // Seven Segment Digit 7
72 oHEX7_DP, // Seven Segment Digit 7 decimal point
73 //////////////////////// LED ////////////////////////
74 oLEDG, // LED Green[8:0]
75 oLEDR, // LED Red[17:0]
76 //////////////////////// UART ////////////////////////
77 oUART_TXD, // UART Transmitter
78 iUART_RXD, // UART Receiver
79 oUART_CTS, // UART Clear To Send
80 iUART_RTS, // UART Requst To Send
81 //////////////////////// IRDA ////////////////////////
82 oIRDA_TXD, // IRDA Transmitter
83 iIRDA_RXD, // IRDA Receiver
84 ///////////////////// SDRAM Interface ////////////////
85 DRAM_DQ, // SDRAM Data bus 32 Bits
86 oDRAM0_A, // SDRAM0 Address bus 13 Bits
87 oDRAM1_A, // SDRAM1 Address bus 13 Bits
88 oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
89 oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
90 oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
91 oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
92 oDRAM0_WE_N, // SDRAM0 Write Enable
93 oDRAM1_WE_N, // SDRAM1 Write Enable
94 oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
95 oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
96 oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
97 oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
98 oDRAM0_CS_N, // SDRAM0 Chip Select
99 oDRAM1_CS_N, // SDRAM1 Chip Select
100 oDRAM0_BA, // SDRAM0 Bank Address
101 oDRAM1_BA, // SDRAM1 Bank Address
102 oDRAM0_CLK, // SDRAM0 Clock
103 oDRAM1_CLK, // SDRAM1 Clock
104 oDRAM0_CKE, // SDRAM0 Clock Enable
105 oDRAM1_CKE, // SDRAM1 Clock Enable
106 //////////////////// Flash Interface ////////////////
107 FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
108 FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
109 oFLASH_A, // FLASH Address bus 26 Bits
110 oFLASH_WE_N, // FLASH Write Enable
111 oFLASH_RST_N, // FLASH Reset
112 oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
113 iFLASH_RY_N, // FLASH Ready/Busy output
114 oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
115 oFLASH_OE_N, // FLASH Output Enable
116 oFLASH_CE_N, // FLASH Chip Enable
117 //////////////////// SRAM Interface ////////////////
118 SRAM_DQ, // SRAM Data Bus 32 Bits
119 SRAM_DPA, // SRAM Parity Data Bus
120 oSRAM_A, // SRAM Address bus 22 Bits
121 oSRAM_ADSC_N, // SRAM Controller Address Status
122 oSRAM_ADSP_N, // SRAM Processor Address Status
123 oSRAM_ADV_N, // SRAM Burst Address Advance
124 oSRAM_BE_N, // SRAM Byte Write Enable
125 oSRAM_CE1_N, // SRAM Chip Enable
126 oSRAM_CE2, // SRAM Chip Enable
127 oSRAM_CE3_N, // SRAM Chip Enable
128 oSRAM_CLK, // SRAM Clock
129 oSRAM_GW_N, // SRAM Global Write Enable
130 oSRAM_OE_N, // SRAM Output Enable
131 oSRAM_WE_N, // SRAM Write Enable
132 //////////////////// ISP1362 Interface ////////////////
133 OTG_D, // ISP1362 Data bus 16 Bits
134 oOTG_A, // ISP1362 Address 2 Bits
135 oOTG_CS_N, // ISP1362 Chip Select
136 oOTG_OE_N, // ISP1362 Read
137 oOTG_WE_N, // ISP1362 Write
138 oOTG_RESET_N, // ISP1362 Reset
139 OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
140 OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
141 iOTG_INT0, // ISP1362 Interrupt 0
142 iOTG_INT1, // ISP1362 Interrupt 1
143 iOTG_DREQ0, // ISP1362 DMA Request 0
144 iOTG_DREQ1, // ISP1362 DMA Request 1
145 oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
146 oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
147 //////////////////// LCD Module 16X2 ////////////////
148 oLCD_ON, // LCD Power ON/OFF
149 oLCD_BLON, // LCD Back Light ON/OFF
150 oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
151 oLCD_EN, // LCD Enable
152 oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
153 LCD_D, // LCD Data bus 8 bits
154 //////////////////// SD_Card Interface ////////////////
155 SD_DAT, // SD Card Data
156 SD_DAT3, // SD Card Data 3
157 SD_CMD, // SD Card Command Signal
158 oSD_CLK, // SD Card Clock
159 //////////////////// I2C ////////////////////////////
160 I2C_SDAT, // I2C Data
161 oI2C_SCLK, // I2C Clock
162 //////////////////// PS2 ////////////////////////////
163 PS2_KBDAT, // PS2 Keyboard Data
164 PS2_KBCLK, // PS2 Keyboard Clock
165 PS2_MSDAT, // PS2 Mouse Data
166 PS2_MSCLK, // PS2 Mouse Clock
167 //////////////////// VGA ////////////////////////////
168 oVGA_CLOCK, // VGA Clock
169 oVGA_HS, // VGA H_SYNC
170 oVGA_VS, // VGA V_SYNC
171 oVGA_BLANK_N, // VGA BLANK
172 oVGA_SYNC_N, // VGA SYNC
173 oVGA_R, // VGA Red[9:0]
174 oVGA_G, // VGA Green[9:0]
175 oVGA_B, // VGA Blue[9:0]
176 //////////// Ethernet Interface ////////////////////////
177 ENET_D, // DM9000A DATA bus 16Bits
178 oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
179 oENET_CS_N, // DM9000A Chip Select
180 oENET_IOW_N, // DM9000A Write
181 oENET_IOR_N, // DM9000A Read
182 oENET_RESET_N, // DM9000A Reset
183 iENET_INT, // DM9000A Interrupt
184 oENET_CLK, // DM9000A Clock 25 MHz
185 //////////////// Audio CODEC ////////////////////////
186 AUD_ADCLRCK, // Audio CODEC ADC LR Clock
187 iAUD_ADCDAT, // Audio CODEC ADC Data
188 AUD_DACLRCK, // Audio CODEC DAC LR Clock
189 oAUD_DACDAT, // Audio CODEC DAC Data
190 AUD_BCLK, // Audio CODEC Bit-Stream Clock
191 oAUD_XCK, // Audio CODEC Chip Clock
192 //////////////// TV Decoder ////////////////////////
193 iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
194 iTD1_D, // TV Decoder1 Data bus 8 bits
195 iTD1_HS, // TV Decoder1 H_SYNC
196 iTD1_VS, // TV Decoder1 V_SYNC
197 oTD1_RESET_N, // TV Decoder1 Reset
198 iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
199 iTD2_D, // TV Decoder2 Data bus 8 bits
200 iTD2_HS, // TV Decoder2 H_SYNC
201 iTD2_VS, // TV Decoder2 V_SYNC
202 oTD2_RESET_N, // TV Decoder2 Reset
203 //////////////////// GPIO ////////////////////////////
204 GPIO_0, // GPIO Connection 0 I/O
205 GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
206 GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
207 GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
208 GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
209 GPIO_1, // GPIO Connection 1 I/O
210 GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
211 GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
212 GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
213 GPIO_CLKOUT_P1 // GPIO Connection 1 Clock Output 1
214
215 );
216
217 //===========================================================================
218 // PARAMETER declarations
219 //===========================================================================
220
221
222 //===========================================================================
223 // PORT declarations
224 //===========================================================================
225 //////////////////////// Clock Input ////////////////////////
226 input iCLK_28; // 28.63636 MHz
227 input iCLK_50; // 50 MHz
228 input iCLK_50_2; // 50 MHz
229 input iCLK_50_3; // 50 MHz
230 input iCLK_50_4; // 50 MHz
231 input iEXT_CLOCK; // External Clock
232 //////////////////////// Push Button ////////////////////////
233 input [3:0] iKEY; // Pushbutton[3:0]
234 //////////////////////// DPDT Switch ////////////////////////
235 input [17:0] iSW; // Toggle Switch[17:0]
236 //////////////////////// 7-SEG Dispaly ////////////////////////
237 output [6:0] oHEX0_D; // Seven Segment Digit 0
238 output oHEX0_DP; // Seven Segment Digit 0 decimal point
239 output [6:0] oHEX1_D; // Seven Segment Digit 1
240 output oHEX1_DP; // Seven Segment Digit 1 decimal point
241 output [6:0] oHEX2_D; // Seven Segment Digit 2
242 output oHEX2_DP; // Seven Segment Digit 2 decimal point
243 output [6:0] oHEX3_D; // Seven Segment Digit 3
244 output oHEX3_DP; // Seven Segment Digit 3 decimal point
245 output [6:0] oHEX4_D; // Seven Segment Digit 4
246 output oHEX4_DP; // Seven Segment Digit 4 decimal point
247 output [6:0] oHEX5_D; // Seven Segment Digit 5
248 output oHEX5_DP; // Seven Segment Digit 5 decimal point
249 output [6:0] oHEX6_D; // Seven Segment Digit 6
250 output oHEX6_DP; // Seven Segment Digit 6 decimal point
251 output [6:0] oHEX7_D; // Seven Segment Digit 7
252 output oHEX7_DP; // Seven Segment Digit 7 decimal point
253 //////////////////////////// LED ////////////////////////////
254 output [8:0] oLEDG; // LED Green[8:0]
255 output [17:0] oLEDR; // LED Red[17:0]
256 //////////////////////////// UART ////////////////////////////
257 output oUART_TXD; // UART Transmitter
258 input iUART_RXD; // UART Receiver
259 output oUART_CTS; // UART Clear To Send
260 input iUART_RTS; // UART Requst To Send
261 //////////////////////////// IRDA ////////////////////////////
262 output oIRDA_TXD; // IRDA Transmitter
263 input iIRDA_RXD; // IRDA Receiver
264 /////////////////////// SDRAM Interface ////////////////////////
265 inout [31:0] DRAM_DQ; // SDRAM Data bus 32 Bits
266 output [12:0] oDRAM0_A; // SDRAM0 Address bus 13 Bits
267 output [12:0] oDRAM1_A; // SDRAM1 Address bus 13 Bits
268 output oDRAM0_LDQM0; // SDRAM0 Low-byte Data Mask
269 output oDRAM1_LDQM0; // SDRAM1 Low-byte Data Mask
270 output oDRAM0_UDQM1; // SDRAM0 High-byte Data Mask
271 output oDRAM1_UDQM1; // SDRAM1 High-byte Data Mask
272 output oDRAM0_WE_N; // SDRAM0 Write Enable
273 output oDRAM1_WE_N; // SDRAM1 Write Enable
274 output oDRAM0_CAS_N; // SDRAM0 Column Address Strobe
275 output oDRAM1_CAS_N; // SDRAM1 Column Address Strobe
276 output oDRAM0_RAS_N; // SDRAM0 Row Address Strobe
277 output oDRAM1_RAS_N; // SDRAM1 Row Address Strobe
278 output oDRAM0_CS_N; // SDRAM0 Chip Select
279 output oDRAM1_CS_N; // SDRAM1 Chip Select
280 output [1:0] oDRAM0_BA; // SDRAM0 Bank Address
281 output [1:0] oDRAM1_BA; // SDRAM1 Bank Address
282 output oDRAM0_CLK; // SDRAM0 Clock
283 output oDRAM1_CLK; // SDRAM1 Clock
284 output oDRAM0_CKE; // SDRAM0 Clock Enable
285 output oDRAM1_CKE; // SDRAM1 Clock Enable
286 //////////////////////// Flash Interface ////////////////////////
287 inout [14:0] FLASH_DQ; // FLASH Data bus 15 Bits (0 to 14)
288 inout FLASH_DQ15_AM1; // FLASH Data bus Bit 15 or Address A-1
289 output [21:0] oFLASH_A; // FLASH Address bus 22 Bits
290 output oFLASH_WE_N; // FLASH Write Enable
291 output oFLASH_RST_N; // FLASH Reset
292 output oFLASH_WP_N; // FLASH Write Protect /Programming Acceleration
293 input iFLASH_RY_N; // FLASH Ready/Busy output
294 output oFLASH_BYTE_N; // FLASH Byte/Word Mode Configuration
295 output oFLASH_OE_N; // FLASH Output Enable
296 output oFLASH_CE_N; // FLASH Chip Enable
297 //////////////////////// SRAM Interface ////////////////////////
298 inout [31:0] SRAM_DQ; // SRAM Data Bus 32 Bits
299 inout [3:0] SRAM_DPA; // SRAM Parity Data Bus
300 output [18:0] oSRAM_A; // SRAM Address bus 21 Bits
301 output oSRAM_ADSC_N; // SRAM Controller Address Status
302 output oSRAM_ADSP_N; // SRAM Processor Address Status
303 output oSRAM_ADV_N; // SRAM Burst Address Advance
304 output [3:0] oSRAM_BE_N; // SRAM Byte Write Enable
305 output oSRAM_CE1_N; // SRAM Chip Enable
306 output oSRAM_CE2; // SRAM Chip Enable
307 output oSRAM_CE3_N; // SRAM Chip Enable
308 output oSRAM_CLK; // SRAM Clock
309 output oSRAM_GW_N; // SRAM Global Write Enable
310 output oSRAM_OE_N; // SRAM Output Enable
311 output oSRAM_WE_N; // SRAM Write Enable
312 //////////////////// ISP1362 Interface ////////////////////////
313 inout [15:0] OTG_D; // ISP1362 Data bus 16 Bits
314 output [1:0] oOTG_A; // ISP1362 Address 2 Bits
315 output oOTG_CS_N; // ISP1362 Chip Select
316 output oOTG_OE_N; // ISP1362 Read
317 output oOTG_WE_N; // ISP1362 Write
318 output oOTG_RESET_N; // ISP1362 Reset
319 inout OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
320 inout OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
321 input iOTG_INT0; // ISP1362 Interrupt 0
322 input iOTG_INT1; // ISP1362 Interrupt 1
323 input iOTG_DREQ0; // ISP1362 DMA Request 0
324 input iOTG_DREQ1; // ISP1362 DMA Request 1
325 output oOTG_DACK0_N; // ISP1362 DMA Acknowledge 0
326 output oOTG_DACK1_N; // ISP1362 DMA Acknowledge 1
327 //////////////////// LCD Module 16X2 ////////////////////////////
328 inout [7:0] LCD_D; // LCD Data bus 8 bits
329 output oLCD_ON; // LCD Power ON/OFF
330 output oLCD_BLON; // LCD Back Light ON/OFF
331 output oLCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
332 output oLCD_EN; // LCD Enable
333 output oLCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
334 //////////////////// SD Card Interface ////////////////////////
335 inout SD_DAT; // SD Card Data
336 inout SD_DAT3; // SD Card Data 3
337 inout SD_CMD; // SD Card Command Signal
338 output oSD_CLK; // SD Card Clock
339 //////////////////////// I2C ////////////////////////////////
340 inout I2C_SDAT; // I2C Data
341 output oI2C_SCLK; // I2C Clock
342 //////////////////////// PS2 ////////////////////////////////
343 inout PS2_KBDAT; // PS2 Keyboard Data
344 inout PS2_KBCLK; // PS2 Keyboard Clock
345 inout PS2_MSDAT; // PS2 Mouse Data
346 inout PS2_MSCLK; // PS2 Mouse Clock
347 //////////////////////// VGA ////////////////////////////
348 output oVGA_CLOCK; // VGA Clock
349 output oVGA_HS; // VGA H_SYNC
350 output oVGA_VS; // VGA V_SYNC
351 output oVGA_BLANK_N; // VGA BLANK
352 output oVGA_SYNC_N; // VGA SYNC
353 output [9:0] oVGA_R; // VGA Red[9:0]
354 output [9:0] oVGA_G; // VGA Green[9:0]
355 output [9:0] oVGA_B; // VGA Blue[9:0]
356 //////////////// Ethernet Interface ////////////////////////////
357 inout [15:0] ENET_D; // DM9000A DATA bus 16Bits
358 output oENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
359 output oENET_CS_N; // DM9000A Chip Select
360 output oENET_IOW_N; // DM9000A Write
361 output oENET_IOR_N; // DM9000A Read
362 output oENET_RESET_N; // DM9000A Reset
363 input iENET_INT; // DM9000A Interrupt
364 output oENET_CLK; // DM9000A Clock 25 MHz
365 //////////////////// Audio CODEC ////////////////////////////
366 inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
367 input iAUD_ADCDAT; // Audio CODEC ADC Data
368 inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
369 output oAUD_DACDAT; // Audio CODEC DAC Data
370 inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
371 output oAUD_XCK; // Audio CODEC Chip Clock
372 //////////////////// TV Devoder ////////////////////////////
373 input iTD1_CLK27; // TV Decoder1 Line_Lock Output Clock
374 input [7:0] iTD1_D; // TV Decoder1 Data bus 8 bits
375 input iTD1_HS; // TV Decoder1 H_SYNC
376 input iTD1_VS; // TV Decoder1 V_SYNC
377 output oTD1_RESET_N; // TV Decoder1 Reset
378 input iTD2_CLK27; // TV Decoder2 Line_Lock Output Clock
379 input [7:0] iTD2_D; // TV Decoder2 Data bus 8 bits
380 input iTD2_HS; // TV Decoder2 H_SYNC
381 input iTD2_VS; // TV Decoder2 V_SYNC
382 output oTD2_RESET_N; // TV Decoder2 Reset
383
384 //////////////////////// GPIO ////////////////////////////////
385 inout [31:0] GPIO_0; // GPIO Connection 0 I/O
386 input GPIO_CLKIN_N0; // GPIO Connection 0 Clock Input 0
387 input GPIO_CLKIN_P0; // GPIO Connection 0 Clock Input 1
388 inout GPIO_CLKOUT_N0; // GPIO Connection 0 Clock Output 0
389 inout GPIO_CLKOUT_P0; // GPIO Connection 0 Clock Output 1
390 inout [31:0] GPIO_1; // GPIO Connection 1 I/O
391 input GPIO_CLKIN_N1; // GPIO Connection 1 Clock Input 0
392 input GPIO_CLKIN_P1; // GPIO Connection 1 Clock Input 1
393 inout GPIO_CLKOUT_N1; // GPIO Connection 1 Clock Output 0
394 inout GPIO_CLKOUT_P1; // GPIO Connection 1 Clock Output 1
395 ///////////////////////////////////////////////////////////////////
396 //=============================================================================
397 // REG/WIRE declarations
398 //=============================================================================
399
400 wire CPU_CLK;
401 wire CPU_RESET;
402 wire CLK_18_4;
403 wire CLK_25;
404
405 // For Audio CODEC
406 wire AUD_CTRL_CLK; // For Audio Controller
407
408 // For ITU-R 656 Decoder
409 wire [15:0] YCbCr;
410 wire [9:0] TV_X;
411 wire TV_DVAL;
412
413 // For VGA Controller
414 wire [9:0] mRed;
415 wire [9:0] mGreen;
416 wire [9:0] mBlue;
417 wire [10:0] VGA_X;
418 wire [10:0] VGA_Y;
419 wire VGA_Read; // VGA data request
420 wire m1VGA_Read; // Read odd field
421 wire m2VGA_Read; // Read even field
422
423 // For YUV 4:2:2 to YUV 4:4:4
424 wire [7:0] mY;
425 wire [7:0] mCb;
426 wire [7:0] mCr;
427
428 // For field select
429 wire [15:0] mYCbCr;
430 wire [15:0] mYCbCr_d;
431 wire [15:0] m1YCbCr;
432 wire [15:0] m2YCbCr;
433 wire [15:0] m3YCbCr;
434
435 // For Delay Timer
436 wire TD_Stable;
437 wire DLY0;
438 wire DLY1;
439 wire DLY2;
440
441 // For Down Sample
442 wire [3:0] Remain;
443 wire [9:0] Quotient;
444
445 wire mDVAL;
446
447 wire [15:0] m4YCbCr;
448 wire [15:0] m5YCbCr;
449 wire [8:0] Tmp1,Tmp2;
450 wire [7:0] Tmp3,Tmp4;
451
452 //=============================================================================
453 // Structural coding
454 //=============================================================================
455
456 // Flash
457 assign oFLASH_RST_N = 1'b1;
458
459 // 16*2 LCD Module
460 assign oLCD_ON = 1'b1; // LCD ON
461 assign oLCD_BLON = 1'b1; // LCD Back Light
462
463 // All inout port turn to tri-state
464 assign SD_DAT = 1'bz;
465 assign AUD_ADCLRCK = AUD_DACLRCK;
466 assign GPIO_0 = 32'hzzzzzzzzz;
467 assign GPIO_1 = 32'hzzzzzzzzz;
468
469 // Disable USB speed select
470 assign OTG_FSPEED = 1'bz;
471 assign OTG_LSPEED = 1'bz;
472
473 // Turn On TV Decoder
474 //assign oTD1_RESET_N = 1'b1;
475 assign oTD2_RESET_N = 1'b1;
476
477 // Set SD Card to SD Mode
478 assign SD_DAT3 = 1'b1;
479
480 // Enable TV Decoder
481 assign oTD1_RESET_N = iKEY[0];
482
483 assign oAUD_XCK = AUD_CTRL_CLK;
484
485 assign oLEDG = VGA_Y;
486 assign oLEDR = VGA_X;
487
488 assign m1VGA_Read = VGA_Y[0] ? 1'b0 : VGA_Read ;
489 assign m2VGA_Read = VGA_Y[0] ? VGA_Read : 1'b0 ;
490 assign mYCbCr_d = !VGA_Y[0] ? m1YCbCr :
491 m2YCbCr ;
492 assign mYCbCr = m5YCbCr;
493
494 assign Tmp1 = m4YCbCr[7:0]+mYCbCr_d[7:0];
495 assign Tmp2 = m4YCbCr[15:8]+mYCbCr_d[15:8];
496 assign Tmp3 = Tmp1[8:2]+m3YCbCr[7:1];
497 assign Tmp4 = Tmp2[8:2]+m3YCbCr[15:9];
498 assign m5YCbCr = {Tmp4,Tmp3};
499
500 // 7 segment LUT
501 SEG7_LUT_8 u0 ( .oSEG0(oHEX0_D),
502 .oSEG1(oHEX1_D),
503 .oSEG2(oHEX2_D),
504 .oSEG3(oHEX3_D),
505 .oSEG4(oHEX4_D),
506 .oSEG5(oHEX5_D),
507 .oSEG6(oHEX6_D),
508 .oSEG7(oHEX7_D),
509 .iDIG(iSW) );
510
511 // TV Decoder Stable Check
512 TD_Detect u2 ( .oTD_Stable(TD_Stable),
513 .iTD_VS(iTD1_VS),
514 .iTD_HS(iTD1_HS),
515 .iRST_N(iKEY[0]) );
516
517 // Reset Delay Timer
518 Reset_Delay u3 ( .iCLK(iCLK_50),
519 .iRST(TD_Stable),
520 .oRST_0(DLY0),
521 .oRST_1(DLY1),
522 .oRST_2(DLY2));
523
524 // ITU-R 656 to YUV 4:2:2
525 ITU_656_Decoder u4 ( // TV Decoder Input
526 .iTD_DATA(iTD1_D),
527 // Position Output
528 .oTV_X(TV_X),
529 // YUV 4:2:2 Output
530 .oYCbCr(YCbCr),
531 .oDVAL(TV_DVAL),
532 // Control Signals
533 .iSwap_CbCr(Quotient[0]),
534 .iSkip(Remain==4'h0),
535 .iRST_N(DLY1),
536 .iCLK_27(iTD1_CLK27) );
537
538 // For Down Sample 720 to 640
539 DIV u5 ( .aclr(!DLY0),
540 .clock(iTD1_CLK27),
541 .denom(4'h9),
542 .numer(TV_X),
543 .quotient(Quotient),
544 .remain(Remain));
545
546 // SDRAM frame buffer
547 Sdram_Control_4Port u6 ( // HOST Side
548 .REF_CLK(iTD1_CLK27),
549 .CLK_18(AUD_CTRL_CLK),
550 .RESET_N(1'b1),
551 // FIFO Write Side 1
552 .WR1_DATA(YCbCr),
553 .WR1(TV_DVAL),
554 .WR1_FULL(WR1_FULL),
555 .WR1_ADDR(0),
556 .WR1_MAX_ADDR(640*507), // 525-18
557 .WR1_LENGTH(9'h80),
558 .WR1_LOAD(!DLY0),
559 .WR1_CLK(iTD1_CLK27),
560 // FIFO Read Side 1
561 .RD1_DATA(m1YCbCr),
562 .RD1(m1VGA_Read),
563 .RD1_ADDR(640*13), // Read odd field and bypess blanking
564 .RD1_MAX_ADDR(640*253),
565 .RD1_LENGTH(9'h80),
566 .RD1_LOAD(!DLY0),
567 .RD1_CLK(iTD1_CLK27),
568 // FIFO Read Side 2
569 .RD2_DATA(m2YCbCr),
570 .RD2(m2VGA_Read),
571 .RD2_ADDR(640*267), // Read even field and bypess blanking
572 .RD2_MAX_ADDR(640*507),
573 .RD2_LENGTH(9'h80),
574 .RD2_LOAD(!DLY0),
575 .RD2_CLK(iTD1_CLK27),
576 // SDRAM Side
577 .SA(oDRAM0_A),
578 .BA({oDRAM0_BA[1],oDRAM0_BA[0]}),
579 .CS_N(oDRAM0_CS_N),
580 .CKE(oDRAM0_CKE),
581 .RAS_N(oDRAM0_RAS_N),
582 .CAS_N(oDRAM0_CAS_N),
583 .WE_N(oDRAM0_WE_N),
584 .DQ(DRAM_DQ),
585 .DQM({oDRAM0_UDQM1,oDRAM0_LDQM0}),
586 .SDR_CLK(oDRAM0_CLK) );
587
588 // YUV 4:2:2 to YUV 4:4:4
589 YUV422_to_444 u7 ( // YUV 4:2:2 Input
590 .iYCbCr(mYCbCr),
591 // YUV 4:4:4 Output
592 .oY(mY),
593 .oCb(mCb),
594 .oCr(mCr),
595 // Control Signals
596 .iX(VGA_X),
597 .iCLK(iTD1_CLK27),
598 .iRST_N(DLY0));
599
600 // YCbCr 8-bit to -10 bit
601 YCbCr2RGB u8 ( // Output Side
602 .Red(mRed),
603 .Green(mGreen),
604 .Blue(mBlue),
605 .oDVAL(mDVAL),
606 // Input Side
607 .iY(mY),
608 .iCb(mCb),
609 .iCr(mCr),
610 .iDVAL(VGA_Read),
611 // Control Signal
612 .iRESET(!DLY2),
613 .iCLK(iTD1_CLK27));
614
615 wire [9:0] Sobel_out;
616
617 Sobel sobel0 (
618 .iCLK(iTD1_CLK27),
619 .iRST_N(DLY2),
620 .iTHRESHOLD(iSW[9:2]),
621 .iDATA(mGreen), // gray
622 .oDATA(Sobel_out)
623 );
624
625
626 // VGA Controller
627 VGA_Ctrl u9 ( // Host Side
628 .iRed(Sobel_out),
629 //.iRed(mRed),
630 .iGreen(Sobel_out),
631 //.iGreen(mGreen),
632 .iBlue(Sobel_out),
633 //.iBlue(mBlue),
634 .oCurrent_X(VGA_X),
635 .oCurrent_Y(VGA_Y),
636 .oRequest(VGA_Read),
637 // VGA Side
638 .oVGA_R(oVGA_R),
639 .oVGA_G(oVGA_G),
640 .oVGA_B(oVGA_B),
641 .oVGA_HS(oVGA_HS),
642 .oVGA_VS(oVGA_VS),
643 .oVGA_SYNC(oVGA_SYNC_N),
644 .oVGA_BLANK(oVGA_BLANK_N),
645 .oVGA_CLOCK(oVGA_CLOCK),
646 // Control Signal
647 .iCLK(iTD1_CLK27),
648 .iRST_N(DLY2) );
649
650 // Line buffer, delay one line
651 Line_Buffer u10 ( .clken(VGA_Read),
652 .clock(iTD1_CLK27),
653 .shiftin(mYCbCr_d),
654 .shiftout(m3YCbCr));
655
656 Line_Buffer u11 ( .clken(VGA_Read),
657 .clock(iTD1_CLK27),
658 .shiftin(m3YCbCr),
659 .shiftout(m4YCbCr));
660
661 AUDIO_DAC u12 ( // Audio Side
662 .oAUD_BCK(AUD_BCLK),
663 .oAUD_DATA(oAUD_DACDAT),
664 .oAUD_LRCK(AUD_DACLRCK),
665 // Control Signals
666 .iSrc_Select(2'b01),
667 .iCLK_18_4(AUD_CTRL_CLK),
668 .iRST_N(DLY1) );
669
670 // Audio CODEC and video decoder setting
671 I2C_AV_Config u1 ( // Host Side
672 .iCLK(iCLK_50),
673 .iRST_N(iKEY[0]),
674 // I2C Side
675 .I2C_SCLK(oI2C_SCLK),
676 .I2C_SDAT(I2C_SDAT) );
677
678
679 endmodule
680
681
2 // Copyright (c) 2007 by Terasic Technologies Inc.
3 // --------------------------------------------------------------------
4 //
5 // Permission:
6 //
7 // Terasic grants permission to use and modify this code for use
8 // in synthesis for all Terasic Development Boards and Altera Development
9 // Kits made by Terasic. Other use of this code, including the selling
10 // ,duplication, or modification of any portion is strictly prohibited.
11 //
12 // Disclaimer:
13 //
14 // This VHDL/Verilog or C/C++ source code is intended as a design reference
15 // which illustrates how these types of functions can be implemented.
16 // It is the user's responsibility to verify their design for
17 // consistency and functionality through the use of formal
18 // verification methods. Terasic provides no warranty regarding the use
19 // or functionality of this code.
20 //
21 // --------------------------------------------------------------------
22 //
23 // Terasic Technologies Inc
24 // 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
25 // HsinChu County, Taiwan
26 // 302
27 //
28 // web: http://www.terasic.com/
29 // email: support@terasic.com
30 //
31 // --------------------------------------------------------------------
32 //
33 // Major Functions: DE2_70 TV Box
34 //
35 // --------------------------------------------------------------------
36 //
37 // Revision History :
38 // --------------------------------------------------------------------
39 // Ver :| Author :| Mod. Date :| Changes Made:
40 // V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
41 // --------------------------------------------------------------------
42
43 module DE2_70_TV
44 (
45 //////////////////// Clock Input ////////////////////
46 iCLK_28, // 28.63636 MHz
47 iCLK_50, // 50 MHz
48 iCLK_50_2, // 50 MHz
49 iCLK_50_3, // 50 MHz
50 iCLK_50_4, // 50 MHz
51 iEXT_CLOCK, // External Clock
52 //////////////////// Push Button ////////////////////
53 iKEY, // Pushbutton[3:0]
54 //////////////////// DPDT Switch ////////////////////
55 iSW, // Toggle Switch[17:0]
56 //////////////////// 7-SEG Dispaly ////////////////////
57 oHEX0_D, // Seven Segment Digit 0
58 oHEX0_DP, // Seven Segment Digit 0 decimal point
59 oHEX1_D, // Seven Segment Digit 1
60 oHEX1_DP, // Seven Segment Digit 1 decimal point
61 oHEX2_D, // Seven Segment Digit 2
62 oHEX2_DP, // Seven Segment Digit 2 decimal point
63 oHEX3_D, // Seven Segment Digit 3
64 oHEX3_DP, // Seven Segment Digit 3 decimal point
65 oHEX4_D, // Seven Segment Digit 4
66 oHEX4_DP, // Seven Segment Digit 4 decimal point
67 oHEX5_D, // Seven Segment Digit 5
68 oHEX5_DP, // Seven Segment Digit 5 decimal point
69 oHEX6_D, // Seven Segment Digit 6
70 oHEX6_DP, // Seven Segment Digit 6 decimal point
71 oHEX7_D, // Seven Segment Digit 7
72 oHEX7_DP, // Seven Segment Digit 7 decimal point
73 //////////////////////// LED ////////////////////////
74 oLEDG, // LED Green[8:0]
75 oLEDR, // LED Red[17:0]
76 //////////////////////// UART ////////////////////////
77 oUART_TXD, // UART Transmitter
78 iUART_RXD, // UART Receiver
79 oUART_CTS, // UART Clear To Send
80 iUART_RTS, // UART Requst To Send
81 //////////////////////// IRDA ////////////////////////
82 oIRDA_TXD, // IRDA Transmitter
83 iIRDA_RXD, // IRDA Receiver
84 ///////////////////// SDRAM Interface ////////////////
85 DRAM_DQ, // SDRAM Data bus 32 Bits
86 oDRAM0_A, // SDRAM0 Address bus 13 Bits
87 oDRAM1_A, // SDRAM1 Address bus 13 Bits
88 oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
89 oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
90 oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
91 oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
92 oDRAM0_WE_N, // SDRAM0 Write Enable
93 oDRAM1_WE_N, // SDRAM1 Write Enable
94 oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
95 oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
96 oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
97 oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
98 oDRAM0_CS_N, // SDRAM0 Chip Select
99 oDRAM1_CS_N, // SDRAM1 Chip Select
100 oDRAM0_BA, // SDRAM0 Bank Address
101 oDRAM1_BA, // SDRAM1 Bank Address
102 oDRAM0_CLK, // SDRAM0 Clock
103 oDRAM1_CLK, // SDRAM1 Clock
104 oDRAM0_CKE, // SDRAM0 Clock Enable
105 oDRAM1_CKE, // SDRAM1 Clock Enable
106 //////////////////// Flash Interface ////////////////
107 FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
108 FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
109 oFLASH_A, // FLASH Address bus 26 Bits
110 oFLASH_WE_N, // FLASH Write Enable
111 oFLASH_RST_N, // FLASH Reset
112 oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
113 iFLASH_RY_N, // FLASH Ready/Busy output
114 oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
115 oFLASH_OE_N, // FLASH Output Enable
116 oFLASH_CE_N, // FLASH Chip Enable
117 //////////////////// SRAM Interface ////////////////
118 SRAM_DQ, // SRAM Data Bus 32 Bits
119 SRAM_DPA, // SRAM Parity Data Bus
120 oSRAM_A, // SRAM Address bus 22 Bits
121 oSRAM_ADSC_N, // SRAM Controller Address Status
122 oSRAM_ADSP_N, // SRAM Processor Address Status
123 oSRAM_ADV_N, // SRAM Burst Address Advance
124 oSRAM_BE_N, // SRAM Byte Write Enable
125 oSRAM_CE1_N, // SRAM Chip Enable
126 oSRAM_CE2, // SRAM Chip Enable
127 oSRAM_CE3_N, // SRAM Chip Enable
128 oSRAM_CLK, // SRAM Clock
129 oSRAM_GW_N, // SRAM Global Write Enable
130 oSRAM_OE_N, // SRAM Output Enable
131 oSRAM_WE_N, // SRAM Write Enable
132 //////////////////// ISP1362 Interface ////////////////
133 OTG_D, // ISP1362 Data bus 16 Bits
134 oOTG_A, // ISP1362 Address 2 Bits
135 oOTG_CS_N, // ISP1362 Chip Select
136 oOTG_OE_N, // ISP1362 Read
137 oOTG_WE_N, // ISP1362 Write
138 oOTG_RESET_N, // ISP1362 Reset
139 OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
140 OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
141 iOTG_INT0, // ISP1362 Interrupt 0
142 iOTG_INT1, // ISP1362 Interrupt 1
143 iOTG_DREQ0, // ISP1362 DMA Request 0
144 iOTG_DREQ1, // ISP1362 DMA Request 1
145 oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
146 oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
147 //////////////////// LCD Module 16X2 ////////////////
148 oLCD_ON, // LCD Power ON/OFF
149 oLCD_BLON, // LCD Back Light ON/OFF
150 oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
151 oLCD_EN, // LCD Enable
152 oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
153 LCD_D, // LCD Data bus 8 bits
154 //////////////////// SD_Card Interface ////////////////
155 SD_DAT, // SD Card Data
156 SD_DAT3, // SD Card Data 3
157 SD_CMD, // SD Card Command Signal
158 oSD_CLK, // SD Card Clock
159 //////////////////// I2C ////////////////////////////
160 I2C_SDAT, // I2C Data
161 oI2C_SCLK, // I2C Clock
162 //////////////////// PS2 ////////////////////////////
163 PS2_KBDAT, // PS2 Keyboard Data
164 PS2_KBCLK, // PS2 Keyboard Clock
165 PS2_MSDAT, // PS2 Mouse Data
166 PS2_MSCLK, // PS2 Mouse Clock
167 //////////////////// VGA ////////////////////////////
168 oVGA_CLOCK, // VGA Clock
169 oVGA_HS, // VGA H_SYNC
170 oVGA_VS, // VGA V_SYNC
171 oVGA_BLANK_N, // VGA BLANK
172 oVGA_SYNC_N, // VGA SYNC
173 oVGA_R, // VGA Red[9:0]
174 oVGA_G, // VGA Green[9:0]
175 oVGA_B, // VGA Blue[9:0]
176 //////////// Ethernet Interface ////////////////////////
177 ENET_D, // DM9000A DATA bus 16Bits
178 oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
179 oENET_CS_N, // DM9000A Chip Select
180 oENET_IOW_N, // DM9000A Write
181 oENET_IOR_N, // DM9000A Read
182 oENET_RESET_N, // DM9000A Reset
183 iENET_INT, // DM9000A Interrupt
184 oENET_CLK, // DM9000A Clock 25 MHz
185 //////////////// Audio CODEC ////////////////////////
186 AUD_ADCLRCK, // Audio CODEC ADC LR Clock
187 iAUD_ADCDAT, // Audio CODEC ADC Data
188 AUD_DACLRCK, // Audio CODEC DAC LR Clock
189 oAUD_DACDAT, // Audio CODEC DAC Data
190 AUD_BCLK, // Audio CODEC Bit-Stream Clock
191 oAUD_XCK, // Audio CODEC Chip Clock
192 //////////////// TV Decoder ////////////////////////
193 iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
194 iTD1_D, // TV Decoder1 Data bus 8 bits
195 iTD1_HS, // TV Decoder1 H_SYNC
196 iTD1_VS, // TV Decoder1 V_SYNC
197 oTD1_RESET_N, // TV Decoder1 Reset
198 iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
199 iTD2_D, // TV Decoder2 Data bus 8 bits
200 iTD2_HS, // TV Decoder2 H_SYNC
201 iTD2_VS, // TV Decoder2 V_SYNC
202 oTD2_RESET_N, // TV Decoder2 Reset
203 //////////////////// GPIO ////////////////////////////
204 GPIO_0, // GPIO Connection 0 I/O
205 GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
206 GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
207 GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
208 GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
209 GPIO_1, // GPIO Connection 1 I/O
210 GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
211 GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
212 GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
213 GPIO_CLKOUT_P1 // GPIO Connection 1 Clock Output 1
214
215 );
216
217 //===========================================================================
218 // PARAMETER declarations
219 //===========================================================================
220
221
222 //===========================================================================
223 // PORT declarations
224 //===========================================================================
225 //////////////////////// Clock Input ////////////////////////
226 input iCLK_28; // 28.63636 MHz
227 input iCLK_50; // 50 MHz
228 input iCLK_50_2; // 50 MHz
229 input iCLK_50_3; // 50 MHz
230 input iCLK_50_4; // 50 MHz
231 input iEXT_CLOCK; // External Clock
232 //////////////////////// Push Button ////////////////////////
233 input [3:0] iKEY; // Pushbutton[3:0]
234 //////////////////////// DPDT Switch ////////////////////////
235 input [17:0] iSW; // Toggle Switch[17:0]
236 //////////////////////// 7-SEG Dispaly ////////////////////////
237 output [6:0] oHEX0_D; // Seven Segment Digit 0
238 output oHEX0_DP; // Seven Segment Digit 0 decimal point
239 output [6:0] oHEX1_D; // Seven Segment Digit 1
240 output oHEX1_DP; // Seven Segment Digit 1 decimal point
241 output [6:0] oHEX2_D; // Seven Segment Digit 2
242 output oHEX2_DP; // Seven Segment Digit 2 decimal point
243 output [6:0] oHEX3_D; // Seven Segment Digit 3
244 output oHEX3_DP; // Seven Segment Digit 3 decimal point
245 output [6:0] oHEX4_D; // Seven Segment Digit 4
246 output oHEX4_DP; // Seven Segment Digit 4 decimal point
247 output [6:0] oHEX5_D; // Seven Segment Digit 5
248 output oHEX5_DP; // Seven Segment Digit 5 decimal point
249 output [6:0] oHEX6_D; // Seven Segment Digit 6
250 output oHEX6_DP; // Seven Segment Digit 6 decimal point
251 output [6:0] oHEX7_D; // Seven Segment Digit 7
252 output oHEX7_DP; // Seven Segment Digit 7 decimal point
253 //////////////////////////// LED ////////////////////////////
254 output [8:0] oLEDG; // LED Green[8:0]
255 output [17:0] oLEDR; // LED Red[17:0]
256 //////////////////////////// UART ////////////////////////////
257 output oUART_TXD; // UART Transmitter
258 input iUART_RXD; // UART Receiver
259 output oUART_CTS; // UART Clear To Send
260 input iUART_RTS; // UART Requst To Send
261 //////////////////////////// IRDA ////////////////////////////
262 output oIRDA_TXD; // IRDA Transmitter
263 input iIRDA_RXD; // IRDA Receiver
264 /////////////////////// SDRAM Interface ////////////////////////
265 inout [31:0] DRAM_DQ; // SDRAM Data bus 32 Bits
266 output [12:0] oDRAM0_A; // SDRAM0 Address bus 13 Bits
267 output [12:0] oDRAM1_A; // SDRAM1 Address bus 13 Bits
268 output oDRAM0_LDQM0; // SDRAM0 Low-byte Data Mask
269 output oDRAM1_LDQM0; // SDRAM1 Low-byte Data Mask
270 output oDRAM0_UDQM1; // SDRAM0 High-byte Data Mask
271 output oDRAM1_UDQM1; // SDRAM1 High-byte Data Mask
272 output oDRAM0_WE_N; // SDRAM0 Write Enable
273 output oDRAM1_WE_N; // SDRAM1 Write Enable
274 output oDRAM0_CAS_N; // SDRAM0 Column Address Strobe
275 output oDRAM1_CAS_N; // SDRAM1 Column Address Strobe
276 output oDRAM0_RAS_N; // SDRAM0 Row Address Strobe
277 output oDRAM1_RAS_N; // SDRAM1 Row Address Strobe
278 output oDRAM0_CS_N; // SDRAM0 Chip Select
279 output oDRAM1_CS_N; // SDRAM1 Chip Select
280 output [1:0] oDRAM0_BA; // SDRAM0 Bank Address
281 output [1:0] oDRAM1_BA; // SDRAM1 Bank Address
282 output oDRAM0_CLK; // SDRAM0 Clock
283 output oDRAM1_CLK; // SDRAM1 Clock
284 output oDRAM0_CKE; // SDRAM0 Clock Enable
285 output oDRAM1_CKE; // SDRAM1 Clock Enable
286 //////////////////////// Flash Interface ////////////////////////
287 inout [14:0] FLASH_DQ; // FLASH Data bus 15 Bits (0 to 14)
288 inout FLASH_DQ15_AM1; // FLASH Data bus Bit 15 or Address A-1
289 output [21:0] oFLASH_A; // FLASH Address bus 22 Bits
290 output oFLASH_WE_N; // FLASH Write Enable
291 output oFLASH_RST_N; // FLASH Reset
292 output oFLASH_WP_N; // FLASH Write Protect /Programming Acceleration
293 input iFLASH_RY_N; // FLASH Ready/Busy output
294 output oFLASH_BYTE_N; // FLASH Byte/Word Mode Configuration
295 output oFLASH_OE_N; // FLASH Output Enable
296 output oFLASH_CE_N; // FLASH Chip Enable
297 //////////////////////// SRAM Interface ////////////////////////
298 inout [31:0] SRAM_DQ; // SRAM Data Bus 32 Bits
299 inout [3:0] SRAM_DPA; // SRAM Parity Data Bus
300 output [18:0] oSRAM_A; // SRAM Address bus 21 Bits
301 output oSRAM_ADSC_N; // SRAM Controller Address Status
302 output oSRAM_ADSP_N; // SRAM Processor Address Status
303 output oSRAM_ADV_N; // SRAM Burst Address Advance
304 output [3:0] oSRAM_BE_N; // SRAM Byte Write Enable
305 output oSRAM_CE1_N; // SRAM Chip Enable
306 output oSRAM_CE2; // SRAM Chip Enable
307 output oSRAM_CE3_N; // SRAM Chip Enable
308 output oSRAM_CLK; // SRAM Clock
309 output oSRAM_GW_N; // SRAM Global Write Enable
310 output oSRAM_OE_N; // SRAM Output Enable
311 output oSRAM_WE_N; // SRAM Write Enable
312 //////////////////// ISP1362 Interface ////////////////////////
313 inout [15:0] OTG_D; // ISP1362 Data bus 16 Bits
314 output [1:0] oOTG_A; // ISP1362 Address 2 Bits
315 output oOTG_CS_N; // ISP1362 Chip Select
316 output oOTG_OE_N; // ISP1362 Read
317 output oOTG_WE_N; // ISP1362 Write
318 output oOTG_RESET_N; // ISP1362 Reset
319 inout OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
320 inout OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
321 input iOTG_INT0; // ISP1362 Interrupt 0
322 input iOTG_INT1; // ISP1362 Interrupt 1
323 input iOTG_DREQ0; // ISP1362 DMA Request 0
324 input iOTG_DREQ1; // ISP1362 DMA Request 1
325 output oOTG_DACK0_N; // ISP1362 DMA Acknowledge 0
326 output oOTG_DACK1_N; // ISP1362 DMA Acknowledge 1
327 //////////////////// LCD Module 16X2 ////////////////////////////
328 inout [7:0] LCD_D; // LCD Data bus 8 bits
329 output oLCD_ON; // LCD Power ON/OFF
330 output oLCD_BLON; // LCD Back Light ON/OFF
331 output oLCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
332 output oLCD_EN; // LCD Enable
333 output oLCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
334 //////////////////// SD Card Interface ////////////////////////
335 inout SD_DAT; // SD Card Data
336 inout SD_DAT3; // SD Card Data 3
337 inout SD_CMD; // SD Card Command Signal
338 output oSD_CLK; // SD Card Clock
339 //////////////////////// I2C ////////////////////////////////
340 inout I2C_SDAT; // I2C Data
341 output oI2C_SCLK; // I2C Clock
342 //////////////////////// PS2 ////////////////////////////////
343 inout PS2_KBDAT; // PS2 Keyboard Data
344 inout PS2_KBCLK; // PS2 Keyboard Clock
345 inout PS2_MSDAT; // PS2 Mouse Data
346 inout PS2_MSCLK; // PS2 Mouse Clock
347 //////////////////////// VGA ////////////////////////////
348 output oVGA_CLOCK; // VGA Clock
349 output oVGA_HS; // VGA H_SYNC
350 output oVGA_VS; // VGA V_SYNC
351 output oVGA_BLANK_N; // VGA BLANK
352 output oVGA_SYNC_N; // VGA SYNC
353 output [9:0] oVGA_R; // VGA Red[9:0]
354 output [9:0] oVGA_G; // VGA Green[9:0]
355 output [9:0] oVGA_B; // VGA Blue[9:0]
356 //////////////// Ethernet Interface ////////////////////////////
357 inout [15:0] ENET_D; // DM9000A DATA bus 16Bits
358 output oENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
359 output oENET_CS_N; // DM9000A Chip Select
360 output oENET_IOW_N; // DM9000A Write
361 output oENET_IOR_N; // DM9000A Read
362 output oENET_RESET_N; // DM9000A Reset
363 input iENET_INT; // DM9000A Interrupt
364 output oENET_CLK; // DM9000A Clock 25 MHz
365 //////////////////// Audio CODEC ////////////////////////////
366 inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
367 input iAUD_ADCDAT; // Audio CODEC ADC Data
368 inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
369 output oAUD_DACDAT; // Audio CODEC DAC Data
370 inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
371 output oAUD_XCK; // Audio CODEC Chip Clock
372 //////////////////// TV Devoder ////////////////////////////
373 input iTD1_CLK27; // TV Decoder1 Line_Lock Output Clock
374 input [7:0] iTD1_D; // TV Decoder1 Data bus 8 bits
375 input iTD1_HS; // TV Decoder1 H_SYNC
376 input iTD1_VS; // TV Decoder1 V_SYNC
377 output oTD1_RESET_N; // TV Decoder1 Reset
378 input iTD2_CLK27; // TV Decoder2 Line_Lock Output Clock
379 input [7:0] iTD2_D; // TV Decoder2 Data bus 8 bits
380 input iTD2_HS; // TV Decoder2 H_SYNC
381 input iTD2_VS; // TV Decoder2 V_SYNC
382 output oTD2_RESET_N; // TV Decoder2 Reset
383
384 //////////////////////// GPIO ////////////////////////////////
385 inout [31:0] GPIO_0; // GPIO Connection 0 I/O
386 input GPIO_CLKIN_N0; // GPIO Connection 0 Clock Input 0
387 input GPIO_CLKIN_P0; // GPIO Connection 0 Clock Input 1
388 inout GPIO_CLKOUT_N0; // GPIO Connection 0 Clock Output 0
389 inout GPIO_CLKOUT_P0; // GPIO Connection 0 Clock Output 1
390 inout [31:0] GPIO_1; // GPIO Connection 1 I/O
391 input GPIO_CLKIN_N1; // GPIO Connection 1 Clock Input 0
392 input GPIO_CLKIN_P1; // GPIO Connection 1 Clock Input 1
393 inout GPIO_CLKOUT_N1; // GPIO Connection 1 Clock Output 0
394 inout GPIO_CLKOUT_P1; // GPIO Connection 1 Clock Output 1
395 ///////////////////////////////////////////////////////////////////
396 //=============================================================================
397 // REG/WIRE declarations
398 //=============================================================================
399
400 wire CPU_CLK;
401 wire CPU_RESET;
402 wire CLK_18_4;
403 wire CLK_25;
404
405 // For Audio CODEC
406 wire AUD_CTRL_CLK; // For Audio Controller
407
408 // For ITU-R 656 Decoder
409 wire [15:0] YCbCr;
410 wire [9:0] TV_X;
411 wire TV_DVAL;
412
413 // For VGA Controller
414 wire [9:0] mRed;
415 wire [9:0] mGreen;
416 wire [9:0] mBlue;
417 wire [10:0] VGA_X;
418 wire [10:0] VGA_Y;
419 wire VGA_Read; // VGA data request
420 wire m1VGA_Read; // Read odd field
421 wire m2VGA_Read; // Read even field
422
423 // For YUV 4:2:2 to YUV 4:4:4
424 wire [7:0] mY;
425 wire [7:0] mCb;
426 wire [7:0] mCr;
427
428 // For field select
429 wire [15:0] mYCbCr;
430 wire [15:0] mYCbCr_d;
431 wire [15:0] m1YCbCr;
432 wire [15:0] m2YCbCr;
433 wire [15:0] m3YCbCr;
434
435 // For Delay Timer
436 wire TD_Stable;
437 wire DLY0;
438 wire DLY1;
439 wire DLY2;
440
441 // For Down Sample
442 wire [3:0] Remain;
443 wire [9:0] Quotient;
444
445 wire mDVAL;
446
447 wire [15:0] m4YCbCr;
448 wire [15:0] m5YCbCr;
449 wire [8:0] Tmp1,Tmp2;
450 wire [7:0] Tmp3,Tmp4;
451
452 //=============================================================================
453 // Structural coding
454 //=============================================================================
455
456 // Flash
457 assign oFLASH_RST_N = 1'b1;
458
459 // 16*2 LCD Module
460 assign oLCD_ON = 1'b1; // LCD ON
461 assign oLCD_BLON = 1'b1; // LCD Back Light
462
463 // All inout port turn to tri-state
464 assign SD_DAT = 1'bz;
465 assign AUD_ADCLRCK = AUD_DACLRCK;
466 assign GPIO_0 = 32'hzzzzzzzzz;
467 assign GPIO_1 = 32'hzzzzzzzzz;
468
469 // Disable USB speed select
470 assign OTG_FSPEED = 1'bz;
471 assign OTG_LSPEED = 1'bz;
472
473 // Turn On TV Decoder
474 //assign oTD1_RESET_N = 1'b1;
475 assign oTD2_RESET_N = 1'b1;
476
477 // Set SD Card to SD Mode
478 assign SD_DAT3 = 1'b1;
479
480 // Enable TV Decoder
481 assign oTD1_RESET_N = iKEY[0];
482
483 assign oAUD_XCK = AUD_CTRL_CLK;
484
485 assign oLEDG = VGA_Y;
486 assign oLEDR = VGA_X;
487
488 assign m1VGA_Read = VGA_Y[0] ? 1'b0 : VGA_Read ;
489 assign m2VGA_Read = VGA_Y[0] ? VGA_Read : 1'b0 ;
490 assign mYCbCr_d = !VGA_Y[0] ? m1YCbCr :
491 m2YCbCr ;
492 assign mYCbCr = m5YCbCr;
493
494 assign Tmp1 = m4YCbCr[7:0]+mYCbCr_d[7:0];
495 assign Tmp2 = m4YCbCr[15:8]+mYCbCr_d[15:8];
496 assign Tmp3 = Tmp1[8:2]+m3YCbCr[7:1];
497 assign Tmp4 = Tmp2[8:2]+m3YCbCr[15:9];
498 assign m5YCbCr = {Tmp4,Tmp3};
499
500 // 7 segment LUT
501 SEG7_LUT_8 u0 ( .oSEG0(oHEX0_D),
502 .oSEG1(oHEX1_D),
503 .oSEG2(oHEX2_D),
504 .oSEG3(oHEX3_D),
505 .oSEG4(oHEX4_D),
506 .oSEG5(oHEX5_D),
507 .oSEG6(oHEX6_D),
508 .oSEG7(oHEX7_D),
509 .iDIG(iSW) );
510
511 // TV Decoder Stable Check
512 TD_Detect u2 ( .oTD_Stable(TD_Stable),
513 .iTD_VS(iTD1_VS),
514 .iTD_HS(iTD1_HS),
515 .iRST_N(iKEY[0]) );
516
517 // Reset Delay Timer
518 Reset_Delay u3 ( .iCLK(iCLK_50),
519 .iRST(TD_Stable),
520 .oRST_0(DLY0),
521 .oRST_1(DLY1),
522 .oRST_2(DLY2));
523
524 // ITU-R 656 to YUV 4:2:2
525 ITU_656_Decoder u4 ( // TV Decoder Input
526 .iTD_DATA(iTD1_D),
527 // Position Output
528 .oTV_X(TV_X),
529 // YUV 4:2:2 Output
530 .oYCbCr(YCbCr),
531 .oDVAL(TV_DVAL),
532 // Control Signals
533 .iSwap_CbCr(Quotient[0]),
534 .iSkip(Remain==4'h0),
535 .iRST_N(DLY1),
536 .iCLK_27(iTD1_CLK27) );
537
538 // For Down Sample 720 to 640
539 DIV u5 ( .aclr(!DLY0),
540 .clock(iTD1_CLK27),
541 .denom(4'h9),
542 .numer(TV_X),
543 .quotient(Quotient),
544 .remain(Remain));
545
546 // SDRAM frame buffer
547 Sdram_Control_4Port u6 ( // HOST Side
548 .REF_CLK(iTD1_CLK27),
549 .CLK_18(AUD_CTRL_CLK),
550 .RESET_N(1'b1),
551 // FIFO Write Side 1
552 .WR1_DATA(YCbCr),
553 .WR1(TV_DVAL),
554 .WR1_FULL(WR1_FULL),
555 .WR1_ADDR(0),
556 .WR1_MAX_ADDR(640*507), // 525-18
557 .WR1_LENGTH(9'h80),
558 .WR1_LOAD(!DLY0),
559 .WR1_CLK(iTD1_CLK27),
560 // FIFO Read Side 1
561 .RD1_DATA(m1YCbCr),
562 .RD1(m1VGA_Read),
563 .RD1_ADDR(640*13), // Read odd field and bypess blanking
564 .RD1_MAX_ADDR(640*253),
565 .RD1_LENGTH(9'h80),
566 .RD1_LOAD(!DLY0),
567 .RD1_CLK(iTD1_CLK27),
568 // FIFO Read Side 2
569 .RD2_DATA(m2YCbCr),
570 .RD2(m2VGA_Read),
571 .RD2_ADDR(640*267), // Read even field and bypess blanking
572 .RD2_MAX_ADDR(640*507),
573 .RD2_LENGTH(9'h80),
574 .RD2_LOAD(!DLY0),
575 .RD2_CLK(iTD1_CLK27),
576 // SDRAM Side
577 .SA(oDRAM0_A),
578 .BA({oDRAM0_BA[1],oDRAM0_BA[0]}),
579 .CS_N(oDRAM0_CS_N),
580 .CKE(oDRAM0_CKE),
581 .RAS_N(oDRAM0_RAS_N),
582 .CAS_N(oDRAM0_CAS_N),
583 .WE_N(oDRAM0_WE_N),
584 .DQ(DRAM_DQ),
585 .DQM({oDRAM0_UDQM1,oDRAM0_LDQM0}),
586 .SDR_CLK(oDRAM0_CLK) );
587
588 // YUV 4:2:2 to YUV 4:4:4
589 YUV422_to_444 u7 ( // YUV 4:2:2 Input
590 .iYCbCr(mYCbCr),
591 // YUV 4:4:4 Output
592 .oY(mY),
593 .oCb(mCb),
594 .oCr(mCr),
595 // Control Signals
596 .iX(VGA_X),
597 .iCLK(iTD1_CLK27),
598 .iRST_N(DLY0));
599
600 // YCbCr 8-bit to -10 bit
601 YCbCr2RGB u8 ( // Output Side
602 .Red(mRed),
603 .Green(mGreen),
604 .Blue(mBlue),
605 .oDVAL(mDVAL),
606 // Input Side
607 .iY(mY),
608 .iCb(mCb),
609 .iCr(mCr),
610 .iDVAL(VGA_Read),
611 // Control Signal
612 .iRESET(!DLY2),
613 .iCLK(iTD1_CLK27));
614
615 wire [9:0] Sobel_out;
616
617 Sobel sobel0 (
618 .iCLK(iTD1_CLK27),
619 .iRST_N(DLY2),
620 .iTHRESHOLD(iSW[9:2]),
621 .iDATA(mGreen), // gray
622 .oDATA(Sobel_out)
623 );
624
625
626 // VGA Controller
627 VGA_Ctrl u9 ( // Host Side
628 .iRed(Sobel_out),
629 //.iRed(mRed),
630 .iGreen(Sobel_out),
631 //.iGreen(mGreen),
632 .iBlue(Sobel_out),
633 //.iBlue(mBlue),
634 .oCurrent_X(VGA_X),
635 .oCurrent_Y(VGA_Y),
636 .oRequest(VGA_Read),
637 // VGA Side
638 .oVGA_R(oVGA_R),
639 .oVGA_G(oVGA_G),
640 .oVGA_B(oVGA_B),
641 .oVGA_HS(oVGA_HS),
642 .oVGA_VS(oVGA_VS),
643 .oVGA_SYNC(oVGA_SYNC_N),
644 .oVGA_BLANK(oVGA_BLANK_N),
645 .oVGA_CLOCK(oVGA_CLOCK),
646 // Control Signal
647 .iCLK(iTD1_CLK27),
648 .iRST_N(DLY2) );
649
650 // Line buffer, delay one line
651 Line_Buffer u10 ( .clken(VGA_Read),
652 .clock(iTD1_CLK27),
653 .shiftin(mYCbCr_d),
654 .shiftout(m3YCbCr));
655
656 Line_Buffer u11 ( .clken(VGA_Read),
657 .clock(iTD1_CLK27),
658 .shiftin(m3YCbCr),
659 .shiftout(m4YCbCr));
660
661 AUDIO_DAC u12 ( // Audio Side
662 .oAUD_BCK(AUD_BCLK),
663 .oAUD_DATA(oAUD_DACDAT),
664 .oAUD_LRCK(AUD_DACLRCK),
665 // Control Signals
666 .iSrc_Select(2'b01),
667 .iCLK_18_4(AUD_CTRL_CLK),
668 .iRST_N(DLY1) );
669
670 // Audio CODEC and video decoder setting
671 I2C_AV_Config u1 ( // Host Side
672 .iCLK(iCLK_50),
673 .iRST_N(iKEY[0]),
674 // I2C Side
675 .I2C_SCLK(oI2C_SCLK),
676 .I2C_SDAT(I2C_SDAT) );
677
678
679 endmodule
680
681
主要的修改如下：
615行
wire [9:0] Sobel_out;
Sobel sobel0 (
.iCLK(iTD1_CLK27),
.iRST_N(DLY2),
.iTHRESHOLD(iSW[9:2]),
.iDATA(mGreen), // gray
.oDATA(Sobel_out)
);
Sobel sobel0 (
.iCLK(iTD1_CLK27),
.iRST_N(DLY2),
.iTHRESHOLD(iSW[9:2]),
.iDATA(mGreen), // gray
.oDATA(Sobel_out)
);
加上Sobel module，與之前的Sobel，這個地方有小改，將iDVAL與oDVAL拿掉，所以連帶的LineBuffer的clock enable我也拿掉了。
626行
// VGA Controller
VGA_Ctrl u9 ( // Host Side
.iRed(Sobel_out),
//.iRed(mRed),
.iGreen(Sobel_out),
//.iGreen(mGreen),
.iBlue(Sobel_out),
//.iBlue(mBlue),
.oCurrent_X(VGA_X),
.oCurrent_Y(VGA_Y),
.oRequest(VGA_Read),
// VGA Side
.oVGA_R(oVGA_R),
.oVGA_G(oVGA_G),
.oVGA_B(oVGA_B),
.oVGA_HS(oVGA_HS),
.oVGA_VS(oVGA_VS),
.oVGA_SYNC(oVGA_SYNC_N),
.oVGA_BLANK(oVGA_BLANK_N),
.oVGA_CLOCK(oVGA_CLOCK),
// Control Signal
.iCLK(iTD1_CLK27),
.iRST_N(DLY2) );
VGA_Ctrl u9 ( // Host Side
.iRed(Sobel_out),
//.iRed(mRed),
.iGreen(Sobel_out),
//.iGreen(mGreen),
.iBlue(Sobel_out),
//.iBlue(mBlue),
.oCurrent_X(VGA_X),
.oCurrent_Y(VGA_Y),
.oRequest(VGA_Read),
// VGA Side
.oVGA_R(oVGA_R),
.oVGA_G(oVGA_G),
.oVGA_B(oVGA_B),
.oVGA_HS(oVGA_HS),
.oVGA_VS(oVGA_VS),
.oVGA_SYNC(oVGA_SYNC_N),
.oVGA_BLANK(oVGA_BLANK_N),
.oVGA_CLOCK(oVGA_CLOCK),
// Control Signal
.iCLK(iTD1_CLK27),
.iRST_N(DLY2) );
將Sobel輸出的信號連至VGA Controller。
完整程式碼下載
DE2_70_TV_sobel.7z
See Also
(原創) 如何實現Real Time的Sobel Edge Detector? (SOC) (Verilog) (Image Processing) (DE2-70) (TRDB-D5M) (TRDB-LTM)
(原創) 如何實現Real Time的Sobel Edge Detector? (SOC) (Verilog) (Image Processing) (DE2) (TRDB-DC2)
