(原創) 哪裡有DE2-70的Nios II reference design可以參考? (SOC) (DE2-70) (Nios II) (SOPC Builder)
拿到DE2-70時，我第一件事情就是找CD內的Nios II reference design，看看哪些ip有變動，但最後發現：DE2-70沒有Nios II的reference design!!
Abstract
拿到DE2-70時，我第一件事情就是找CD內的Nios II reference design，看看哪些ip有變動，但最後發現：DE2-70沒有Nios II的reference design!!
Introduction
使用環境：Quartus II 8.0 + DE2-70 (Cyclone II EP2C70F896C6N)
DE2 CD內Nios II reference design一直是大家研究Nios II的終極範本，自己用SOPC Builder兜出來的Nios II不能動，一定是因為一些參數、timing設定不對，只要將DE2的Nios II reference design叫出來好好研究，最後幾乎都能解決。
在DE2-70，的確多了不少有趣的範例，但問題是：這些範例大都是硬體的RTL code，若想研究Verilog練RTL，這些範例非常有用，但Nios II的範例相對就很少，對於想要用DE2-70玩Nios II的人，連reference design都沒有，實在很頭痛。
所幸在CD中的\Demonstrations\DE2_70_demonstrations\DE2_70_NET\範例，是少數帶有Nios II的範例，我以此範例為藍本加以修改，整理出接近DE2 reference design的DE2_70_NIOS 1.0，這個範例已經驅動了DE2-70所有的周邊(當然沒有包括CMOS與LTM)，這對於DE2-70的Nios II與SOPC Builder初學者會有幫助。
DE2_70_NIOS.v / Verilog
1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : DE2_70_NIOS.v
5 Compiler : Quartus II 8.0
6 Description : DE2_70_NIOS reference design
7 Release : 10/19/2008 1.0
8 */
9
10 module DE2_70_NIOS (
11 input iCLK_28, // 28.63636 MHz
12 input iCLK_50, // 50 MHz
13 input iCLK_50_2, // 50 MHz
14 input iCLK_50_3, // 50 MHz
15 input iCLK_50_4, // 50 MHz
16 input iEXT_CLOCK, // External Clock
17 ////////////////////////////// Push Button ////////////////////////
18 input [3:0] iKEY, // Pushbutton[3:0]
19 ////////////////////////////// DPDT Switch ////////////////////////
20 input [17:0] iSW, // Toggle Switch[17:0]
21 ////////////////////////////// 7-SEG Dispaly ////////////////////////
22 output [6:0] oHEX0_D, // Seven Segment Digit 0
23 output oHEX0_DP, // Seven Segment Digit 0 decimal point
24 output [6:0] oHEX1_D, // Seven Segment Digit 1
25 output oHEX1_DP, // Seven Segment Digit 1 decimal point
26 output [6:0] oHEX2_D, // Seven Segment Digit 2
27 output oHEX2_DP, // Seven Segment Digit 2 decimal point
28 output [6:0] oHEX3_D, // Seven Segment Digit 3
29 output oHEX3_DP, // Seven Segment Digit 3 decimal point
30 output [6:0] oHEX4_D, // Seven Segment Digit 4
31 output oHEX4_DP, // Seven Segment Digit 4 decimal point
32 output [6:0] oHEX5_D, // Seven Segment Digit 5
33 output oHEX5_DP, // Seven Segment Digit 5 decimal point
34 output [6:0] oHEX6_D, // Seven Segment Digit 6
35 output oHEX6_DP, // Seven Segment Digit 6 decimal point
36 output [6:0] oHEX7_D, // Seven Segment Digit 7
37 output oHEX7_DP, // Seven Segment Digit 7 decimal point
38 //////////////////////////////// LED ////////////////////////////
39 output [8:0] oLEDG, // LED Green[8:0]
40 output [17:0] oLEDR, // LED Red[17:0]
41 //////////////////////////////// UART ////////////////////////////
42 output oUART_TXD, // UART Transmitter
43 input iUART_RXD, // UART Receiver
44 output oUART_CTS, // UART Clear To Send
45 input iUART_RTS, // UART Requst To Send
46 //////////////////////////////// IRDA ////////////////////////////
47 output oIRDA_TXD, // IRDA Transmitter
48 input iIRDA_RXD, // IRDA Receiver
49 //////////////////////////////// SDRAM Interface ////////////////////////
50 inout [31:0] DRAM_DQ, // SDRAM Data bus 32 Bits
51 output [12:0] oDRAM0_A, // SDRAM0 Address bus 12 Bits
52 output [12:0] oDRAM1_A, // SDRAM1 Address bus 12 Bits
53 output oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
54 output oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
55 output oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
56 output oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
57 output oDRAM0_WE_N, // SDRAM0 Write Enable
58 output oDRAM1_WE_N, // SDRAM1 Write Enable
59 output oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
60 output oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
61 output oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
62 output oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
63 output oDRAM0_CS_N, // SDRAM0 Chip Select
64 output oDRAM1_CS_N, // SDRAM1 Chip Select
65 output [1:0] oDRAM0_BA, // SDRAM0 Bank Address
66 output [1:0] oDRAM1_BA, // SDRAM1 Bank Address
67 output oDRAM0_CLK, // SDRAM0 Clock
68 output oDRAM1_CLK, // SDRAM0 Clock
69 output oDRAM0_CKE, // SDRAM0 Clock Enable
70 output oDRAM1_CKE, // SDRAM1 Clock Enable
71 //////////////////////////////// Flash Interface ////////////////////////
72 inout [14:0] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
73 inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
74 output [25:0] oFLASH_A, // FLASH Address bus 26 Bits
75 output oFLASH_WE_N, // FLASH Write Enable
76 output oFLASH_RST_N, // FLASH Reset
77 output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
78 input iFLASH_RY_N, // FLASH Ready/Busy output
79 output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
80 output oFLASH_OE_N, // FLASH Output Enable
81 output oFLASH_CE_N, // FLASH Chip Enable
82 //////////////////////////////// SRAM Interface ////////////////////////
83 inout [31:0] SRAM_DQ, // SRAM Data Bus 32 Bits
84 inout [3:0] SRAM_DPA, // SRAM Parity Data Bus
85 output [20:0] oSRAM_A, // SRAM Address bus 21 Bits
86 output oSRAM_ADSC_N, // RAM Controller Address Status
87 output oSRAM_ADSP_N, // SRAM Processor Address Status
88 output oSRAM_ADV_N, // SRAM Burst Address Advance
89 output [3:0] oSRAM_BE_N, // SRAM Byte Write Enable
90 output oSRAM_CE1_N, // SRAM Chip Enable
91 output oSRAM_CE2, // SRAM Chip Enable
92 output oSRAM_CE3_N, // SRAM Chip Enable
93 output oSRAM_CLK, // SRAM Clock
94 output oSRAM_GW_N, // SRAM Global Write Enable
95 output oSRAM_OE_N, // SRAM Output Enable
96 output oSRAM_WE_N, // SRAM Write Enable
97 //////////////////////////////// ISP1362 Interface ////////////////////////
98 inout [15:0] OTG_D, // ISP1362 Data bus 16 Bits
99 output [1:0] oOTG_A, // ISP1362 Address 2 Bits
100 output oOTG_CS_N, // ISP1362 Chip Select
101 output oOTG_OE_N, // ISP1362 Read
102 output oOTG_WE_N, // ISP1362 Write
103 output oOTG_RESET_N, // ISP1362 Reset
104 inout OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
105 inout OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
106 input iOTG_INT0, // ISP1362 Interrupt 0
107 input iOTG_INT1, // ISP1362 Interrupt 1
108 input iOTG_DREQ0, // ISP1362 DMA Request 0
109 input iOTG_DREQ1, // ISP1362 DMA Request 1
110 output oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
111 output oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
112 //////////////////////////////// LCD Module 16X2 ////////////////////////////
113 inout [7:0] LCD_D, // LCD Data bus 8 bits
114 output oLCD_ON, // LCD Power ON/OFF
115 output oLCD_BLON, // LCD Back Light ON/OFF
116 output oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
117 output oLCD_EN, // LCD Enable
118 output oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
119 //////////////////////////////// SD Card Interface ////////////////////////
120 inout SD_DAT, // SD Card Data
121 inout SD_DAT3, // SD Card Data 3
122 inout SD_CMD, // SD Card Command Signal
123 output oSD_CLK, // SD Card Clock
124 //////////////////////////////// I2C ////////////////////////////////
125 inout I2C_SDAT, // I2C Data
126 output oI2C_SCLK, // I2C Clock
127 //////////////////////////////// PS2 ////////////////////////////
128 inout PS2_KBDAT, // PS2 Keyboard Data
129 inout PS2_KBCLK, // PS2 Keyboard Clock
130 inout PS2_MSDAT, // PS2 Mouse Data
131 inout PS2_MSCLK, // PS2 Mouse Clock
132 //////////////////////////////// VGA ////////////////////////////
133 output oVGA_CLOCK, // VGA Clock
134 output oVGA_HS, // VGA H_SYNC
135 output oVGA_VS, // VGA V_SYNC
136 output oVGA_BLANK_N, // VGA BLANK
137 output oVGA_SYNC_N, // VGA SYNC
138 output [9:0] oVGA_R, // VGA Red[9:0]
139 output [9:0] oVGA_G, // VGA Green[9:0]
140 output [9:0] oVGA_B, // VGA Blue[9:0]
141 //////////////////////////////// Ethernet Interface ////////////////////////////
142 inout [15:0] ENET_D, // DM9000A DATA bus 16Bits
143 output oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
144 output oENET_CS_N, // DM9000A Chip Select
145 output oENET_IOW_N, // DM9000A Write
146 output oENET_IOR_N, // DM9000A Read
147 output oENET_RESET_N, // DM9000A Reset
148 input iENET_INT, // DM9000A Interrupt
149 output oENET_CLK, // DM9000A Clock 25 MHz
150 //////////////////////////////// Audio CODEC ////////////////////////////
151 inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
152 input iAUD_ADCDAT, // Audio CODEC ADC Data
153 inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
154 output oAUD_DACDAT, // Audio CODEC DAC Data
155 inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
156 output oAUD_XCK, // Audio CODEC Chip Clock
157 //////////////////////////////// TV Devoder ////////////////////////////
158 input iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
159 input [7:0] iTD1_D, // TV Decoder1 Data bus 8 bits
160 input iTD1_HS, // TV Decoder1 H_SYNC
161 input iTD1_VS, // TV Decoder1 V_SYNC
162 output oTD1_RESET_N, // TV Decoder1 Reset
163 input iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
164 input [7:0] iTD2_D, // TV Decoder2 Data bus 8 bits
165 input iTD2_HS, // TV Decoder2 H_SYNC
166 input iTD2_VS, // TV Decoder2 V_SYNC
167 output oTD2_RESET_N, // TV Decoder2 Reset
168 //////////////////////////////// GPIO ////////////////////////////////
169 inout [31:0] GPIO_0, // GPIO Connection 0 I/O
170 input GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
171 input GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
172 output GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
173 output GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
174 inout [31:0] GPIO_1, // GPIO Connection 1 I/O
175 input GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
176 input GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
177 output GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
178 output GPIO_CLKOUT_P1 // PIO Connection 1 Clock Output 1
179 );
180
181 // All inout port turn to tri-state
182 assign SD_DAT = 1'bz;
183 assign GPIO_0 = 32'hzzzzzzzzz;
184 assign GPIO_1 = 32'hzzzzzzzzz;
185 assign AUD_ADCLRCK = 1'bz;
186
187 // Turn On TV Decoder
188 assign oTD1_RESET_N = 1'bz;
189 assign oTD2_RESET_N = 1'bz;
190
191 // Flash
192 assign FL_RST_N = 1'b1;
193
194 // 16*2 LCD Module
195 assign oLCD_ON = 1'b1; // LCD ON
196 assign oLCD_BLON = 1'b1; // LCD Back Light
197
198 // Disable USB speed select
199 assign OTG_FSPEED = 1'bz;
200 assign OTG_LSPEED = 1'bz;
201
202 // FLASH
203 wire FLASH_16BIT_IP_A0;
204 assign oFLASH_BYTE_N = 1'b1; // FLASH Byte/Word Mode Configuration
205 assign oFLASH_RST_N = 1'b1; // FLASH Reset
206 assign oFLASH_WP_N = 1'b1; // FLASH Write Protect /Programming Acceleration
207
208 // SSRAM
209 wire [1:0] SRAM_DUMMY_ADDR; // used to ignore the A0/A1 pin from Cypress SSRAM IP core
210 assign oSRAM_ADSP_N = 1'b1; // SRAM Processor Address Status
211 assign oSRAM_ADV_N = 1'b1; // SRAM Burst Address Advance
212 assign oSRAM_CE2 = ~oSRAM_CE1_N; // SRAM Chip Enable
213 assign oSRAM_CE3_N = oSRAM_CE1_N; // SRAM Chip Enable
214 assign oSRAM_GW_N = 1'b1; // SRAM Global Write Enable
215 assign oSRAM_CLK = oDRAM0_CLK;
216
217 // SDRAM
218 // the sdram is shahred with rtl and nios
219 assign oDRAM1_CLK = oDRAM0_CLK;
220
221 // USB
222 assign OTG_FSPEED = 1'bz; // USB Full Speed, 0 = Enable, Z = Disable
223 assign OTG_LSPEED = 1'bz; // USB Low Speed, 0 = Enable, Z = Disable
224
225 // Clock 25MHz
226 reg iCLK_25;
227
228 always@(posedge iCLK_50)
229 iCLK_25 <= ~iCLK_25;
230
231 // NIOS CPU
232 wire CPU_CLK;
233 wire CPU_RESET_N;
234
235 Reset_Delay delay0 (
236 .iRST(iKEY[0]),
237 .iCLK(iCLK_50),
238 .oRESET(CPU_RESET_N)
239 );
240
241 // NIOS II system
242 nios_ii nios_ii0 (
243 // 1) global signals:
244 .clk_50(iCLK_50),
245 .pll_c0_system(CPU_CLK),
246 .pll_c1_memory(oDRAM0_CLK),
247 .pll_c2_audio(oAUD_XCK),
248 .reset_n(CPU_RESET_N),
249 .clk_25(iCLK_25),
250 // the_DM9000A_IF_0
251 .avs_s1_export_ENET_CLK_from_the_DM9000A(oENET_CLK),
252 .avs_s1_export_ENET_CMD_from_the_DM9000A(oENET_CMD),
253 .avs_s1_export_ENET_CS_N_from_the_DM9000A(oENET_CS_N),
254 .avs_s1_export_ENET_DATA_to_and_from_the_DM9000A(ENET_D),
255 .avs_s1_export_ENET_INT_to_the_DM9000A(iENET_INT),
256 .avs_s1_export_ENET_RD_N_from_the_DM9000A(oENET_IOR_N),
257 .avs_s1_export_ENET_RST_N_from_the_DM9000A(oENET_RESET_N),
258 .avs_s1_export_ENET_WR_N_from_the_DM9000A(oENET_IOW_N),
259 // the_ISP1362
260 .avs_hc_export_OTG_ADDR_from_the_ISP1362(oOTG_A),
261 .avs_hc_export_OTG_CS_N_from_the_ISP1362(oOTG_CS_N),
262 .avs_hc_export_OTG_DATA_to_and_from_the_ISP1362(OTG_D),
263 .avs_hc_export_OTG_INT0_to_the_ISP1362(iOTG_INT0),
264 .avs_hc_export_OTG_RD_N_from_the_ISP1362(oOTG_OE_N),
265 .avs_hc_export_OTG_RST_N_from_the_ISP1362(oOTG_RESET_N),
266 .avs_hc_export_OTG_WR_N_from_the_ISP1362(oOTG_WE_N),
267 .avs_dc_export_OTG_INT1_to_the_ISP1362(iOTG_INT1),
268 // the_audio
269 .avs_s1_export_BCLK_to_the_AUDIO(AUD_BCLK),
270 .avs_s1_export_DACLRC_to_the_AUDIO(AUD_DACLRCK),
271 .avs_s1_export_DACDAT_from_the_AUDIO(oAUD_DACDAT),
272 .avs_s1_export_ADCLRC_to_the_AUDIO(AUD_ADCLRCK),
273 .avs_s1_export_ADCDAT_to_the_AUDIO(iAUD_ADCDAT),
274 // the_i2c_sclk
275 .out_port_from_the_i2c_sclk(oI2C_SCLK),
276 // the_i2c_sdat
277 .bidir_port_to_and_from_the_i2c_sdat(I2C_SDAT),
278 // the_lcd
279 .LCD_E_from_the_lcd(oLCD_EN),
280 .LCD_RS_from_the_lcd(oLCD_RS),
281 .LCD_RW_from_the_lcd(oLCD_RW),
282 .LCD_data_to_and_from_the_lcd(LCD_D),
283 // the_pio_button
284 .in_port_to_the_pio_button(iKEY),
285 // the_pio_green_led
286 .out_port_from_the_pio_green_led(oLEDG),
287 // the_pio_red_led
288 .out_port_from_the_pio_red_led(oLEDR),
289 // the_seg7
290 .avs_s1_export_seg7_from_the_SEG7({oHEX7_DP, oHEX7_D, oHEX6_DP, oHEX6_D, oHEX5_DP,
291 oHEX5_D, oHEX4_DP,oHEX4_D, oHEX3_DP, oHEX3_D, oHEX2_DP, oHEX2_D, oHEX1_DP, oHEX1_D,
292 oHEX0_DP, oHEX0_D}),
293 // the_pio_switch
294 .in_port_to_the_pio_switch(iSW),
295 // the_sd_clk
296 .out_port_from_the_sd_clk(oSD_CLK),
297 // the_sd_cmd
298 .bidir_port_to_and_from_the_sd_cmd(SD_CMD),
299 // the_sd_dat
300 .bidir_port_to_and_from_the_sd_dat(SD_DAT),
301 // the_sd_dat3
302 .bidir_port_to_and_from_the_sd_dat3(SD_DAT3),
303 // the_sdram (u1)
304 .zs_addr_from_the_sdram_u1(oDRAM0_A),
305 .zs_ba_from_the_sdram_u1(oDRAM0_BA),
306 .zs_cas_n_from_the_sdram_u1(oDRAM0_CAS_N),
307 .zs_cke_from_the_sdram_u1(oDRAM0_CKE),
308 .zs_cs_n_from_the_sdram_u1(oDRAM0_CS_N),
309 .zs_dq_to_and_from_the_sdram_u1(DRAM_DQ[15:0]),
310 .zs_dqm_from_the_sdram_u1({oDRAM0_UDQM1,oDRAM0_LDQM0}),
311 .zs_ras_n_from_the_sdram_u1(oDRAM0_RAS_N),
312 .zs_we_n_from_the_sdram_u1(oDRAM0_WE_N),
313 // the_sdram (u2)
314 .zs_addr_from_the_sdram_u2(oDRAM1_A),
315 .zs_ba_from_the_sdram_u2(oDRAM1_BA),
316 .zs_cas_n_from_the_sdram_u2(oDRAM1_CAS_N),
317 .zs_cke_from_the_sdram_u2(oDRAM1_CKE),
318 .zs_cs_n_from_the_sdram_u2(oDRAM1_CS_N),
319 .zs_dq_to_and_from_the_sdram_u2(DRAM_DQ[31:16]),
320 .zs_dqm_from_the_sdram_u2({oDRAM1_UDQM1,oDRAM1_LDQM0}),
321 .zs_ras_n_from_the_sdram_u2(oDRAM1_RAS_N),
322 .zs_we_n_from_the_sdram_u2(oDRAM1_WE_N),
323 // the_tristate_bridge_avalon_slave (flash)
324 .address_to_the_cfi_flash({oFLASH_A[21:0],FLASH_16BIT_IP_A0}),
325 .data_to_and_from_the_cfi_flash({FLASH_DQ15_AM1,FLASH_DQ}),
326 .read_n_to_the_cfi_flash(oFLASH_OE_N),
327 .select_n_to_the_cfi_flash(oFLASH_CE_N),
328 .write_n_to_the_cfi_flash(oFLASH_WE_N),
329 // the_tristate_bridge_1_avalon_slave (ssram)
330 .address_to_the_ssram({oSRAM_A[17:0],SRAM_DUMMY_ADDR}),
331 .adsc_n_to_the_ssram(oSRAM_ADSC_N),
332 .bw_n_to_the_ssram(oSRAM_BE_N),
333 .bwe_n_to_the_ssram(oSRAM_WE_N),
334 .chipenable1_n_to_the_ssram(oSRAM_CE1_N),
335 .data_to_and_from_the_ssram((SRAM_DQ)),
336 .outputenable_n_to_the_ssram(oSRAM_OE_N),
337 // the_uart
338 .cts_n_to_the_uart(oUART_CTS),
339 .rts_n_from_the_uart(iUART_RTS),
340 .rxd_to_the_uart(iUART_RXD),
341 .txd_from_the_uart(oUART_TXD),
342 );
343
344 endmodule
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : DE2_70_NIOS.v
5 Compiler : Quartus II 8.0
6 Description : DE2_70_NIOS reference design
7 Release : 10/19/2008 1.0
8 */
9
10 module DE2_70_NIOS (
11 input iCLK_28, // 28.63636 MHz
12 input iCLK_50, // 50 MHz
13 input iCLK_50_2, // 50 MHz
14 input iCLK_50_3, // 50 MHz
15 input iCLK_50_4, // 50 MHz
16 input iEXT_CLOCK, // External Clock
17 ////////////////////////////// Push Button ////////////////////////
18 input [3:0] iKEY, // Pushbutton[3:0]
19 ////////////////////////////// DPDT Switch ////////////////////////
20 input [17:0] iSW, // Toggle Switch[17:0]
21 ////////////////////////////// 7-SEG Dispaly ////////////////////////
22 output [6:0] oHEX0_D, // Seven Segment Digit 0
23 output oHEX0_DP, // Seven Segment Digit 0 decimal point
24 output [6:0] oHEX1_D, // Seven Segment Digit 1
25 output oHEX1_DP, // Seven Segment Digit 1 decimal point
26 output [6:0] oHEX2_D, // Seven Segment Digit 2
27 output oHEX2_DP, // Seven Segment Digit 2 decimal point
28 output [6:0] oHEX3_D, // Seven Segment Digit 3
29 output oHEX3_DP, // Seven Segment Digit 3 decimal point
30 output [6:0] oHEX4_D, // Seven Segment Digit 4
31 output oHEX4_DP, // Seven Segment Digit 4 decimal point
32 output [6:0] oHEX5_D, // Seven Segment Digit 5
33 output oHEX5_DP, // Seven Segment Digit 5 decimal point
34 output [6:0] oHEX6_D, // Seven Segment Digit 6
35 output oHEX6_DP, // Seven Segment Digit 6 decimal point
36 output [6:0] oHEX7_D, // Seven Segment Digit 7
37 output oHEX7_DP, // Seven Segment Digit 7 decimal point
38 //////////////////////////////// LED ////////////////////////////
39 output [8:0] oLEDG, // LED Green[8:0]
40 output [17:0] oLEDR, // LED Red[17:0]
41 //////////////////////////////// UART ////////////////////////////
42 output oUART_TXD, // UART Transmitter
43 input iUART_RXD, // UART Receiver
44 output oUART_CTS, // UART Clear To Send
45 input iUART_RTS, // UART Requst To Send
46 //////////////////////////////// IRDA ////////////////////////////
47 output oIRDA_TXD, // IRDA Transmitter
48 input iIRDA_RXD, // IRDA Receiver
49 //////////////////////////////// SDRAM Interface ////////////////////////
50 inout [31:0] DRAM_DQ, // SDRAM Data bus 32 Bits
51 output [12:0] oDRAM0_A, // SDRAM0 Address bus 12 Bits
52 output [12:0] oDRAM1_A, // SDRAM1 Address bus 12 Bits
53 output oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
54 output oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
55 output oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
56 output oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
57 output oDRAM0_WE_N, // SDRAM0 Write Enable
58 output oDRAM1_WE_N, // SDRAM1 Write Enable
59 output oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
60 output oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
61 output oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
62 output oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
63 output oDRAM0_CS_N, // SDRAM0 Chip Select
64 output oDRAM1_CS_N, // SDRAM1 Chip Select
65 output [1:0] oDRAM0_BA, // SDRAM0 Bank Address
66 output [1:0] oDRAM1_BA, // SDRAM1 Bank Address
67 output oDRAM0_CLK, // SDRAM0 Clock
68 output oDRAM1_CLK, // SDRAM0 Clock
69 output oDRAM0_CKE, // SDRAM0 Clock Enable
70 output oDRAM1_CKE, // SDRAM1 Clock Enable
71 //////////////////////////////// Flash Interface ////////////////////////
72 inout [14:0] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
73 inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
74 output [25:0] oFLASH_A, // FLASH Address bus 26 Bits
75 output oFLASH_WE_N, // FLASH Write Enable
76 output oFLASH_RST_N, // FLASH Reset
77 output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
78 input iFLASH_RY_N, // FLASH Ready/Busy output
79 output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
80 output oFLASH_OE_N, // FLASH Output Enable
81 output oFLASH_CE_N, // FLASH Chip Enable
82 //////////////////////////////// SRAM Interface ////////////////////////
83 inout [31:0] SRAM_DQ, // SRAM Data Bus 32 Bits
84 inout [3:0] SRAM_DPA, // SRAM Parity Data Bus
85 output [20:0] oSRAM_A, // SRAM Address bus 21 Bits
86 output oSRAM_ADSC_N, // RAM Controller Address Status
87 output oSRAM_ADSP_N, // SRAM Processor Address Status
88 output oSRAM_ADV_N, // SRAM Burst Address Advance
89 output [3:0] oSRAM_BE_N, // SRAM Byte Write Enable
90 output oSRAM_CE1_N, // SRAM Chip Enable
91 output oSRAM_CE2, // SRAM Chip Enable
92 output oSRAM_CE3_N, // SRAM Chip Enable
93 output oSRAM_CLK, // SRAM Clock
94 output oSRAM_GW_N, // SRAM Global Write Enable
95 output oSRAM_OE_N, // SRAM Output Enable
96 output oSRAM_WE_N, // SRAM Write Enable
97 //////////////////////////////// ISP1362 Interface ////////////////////////
98 inout [15:0] OTG_D, // ISP1362 Data bus 16 Bits
99 output [1:0] oOTG_A, // ISP1362 Address 2 Bits
100 output oOTG_CS_N, // ISP1362 Chip Select
101 output oOTG_OE_N, // ISP1362 Read
102 output oOTG_WE_N, // ISP1362 Write
103 output oOTG_RESET_N, // ISP1362 Reset
104 inout OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
105 inout OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
106 input iOTG_INT0, // ISP1362 Interrupt 0
107 input iOTG_INT1, // ISP1362 Interrupt 1
108 input iOTG_DREQ0, // ISP1362 DMA Request 0
109 input iOTG_DREQ1, // ISP1362 DMA Request 1
110 output oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
111 output oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
112 //////////////////////////////// LCD Module 16X2 ////////////////////////////
113 inout [7:0] LCD_D, // LCD Data bus 8 bits
114 output oLCD_ON, // LCD Power ON/OFF
115 output oLCD_BLON, // LCD Back Light ON/OFF
116 output oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
117 output oLCD_EN, // LCD Enable
118 output oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
119 //////////////////////////////// SD Card Interface ////////////////////////
120 inout SD_DAT, // SD Card Data
121 inout SD_DAT3, // SD Card Data 3
122 inout SD_CMD, // SD Card Command Signal
123 output oSD_CLK, // SD Card Clock
124 //////////////////////////////// I2C ////////////////////////////////
125 inout I2C_SDAT, // I2C Data
126 output oI2C_SCLK, // I2C Clock
127 //////////////////////////////// PS2 ////////////////////////////
128 inout PS2_KBDAT, // PS2 Keyboard Data
129 inout PS2_KBCLK, // PS2 Keyboard Clock
130 inout PS2_MSDAT, // PS2 Mouse Data
131 inout PS2_MSCLK, // PS2 Mouse Clock
132 //////////////////////////////// VGA ////////////////////////////
133 output oVGA_CLOCK, // VGA Clock
134 output oVGA_HS, // VGA H_SYNC
135 output oVGA_VS, // VGA V_SYNC
136 output oVGA_BLANK_N, // VGA BLANK
137 output oVGA_SYNC_N, // VGA SYNC
138 output [9:0] oVGA_R, // VGA Red[9:0]
139 output [9:0] oVGA_G, // VGA Green[9:0]
140 output [9:0] oVGA_B, // VGA Blue[9:0]
141 //////////////////////////////// Ethernet Interface ////////////////////////////
142 inout [15:0] ENET_D, // DM9000A DATA bus 16Bits
143 output oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
144 output oENET_CS_N, // DM9000A Chip Select
145 output oENET_IOW_N, // DM9000A Write
146 output oENET_IOR_N, // DM9000A Read
147 output oENET_RESET_N, // DM9000A Reset
148 input iENET_INT, // DM9000A Interrupt
149 output oENET_CLK, // DM9000A Clock 25 MHz
150 //////////////////////////////// Audio CODEC ////////////////////////////
151 inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
152 input iAUD_ADCDAT, // Audio CODEC ADC Data
153 inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
154 output oAUD_DACDAT, // Audio CODEC DAC Data
155 inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
156 output oAUD_XCK, // Audio CODEC Chip Clock
157 //////////////////////////////// TV Devoder ////////////////////////////
158 input iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
159 input [7:0] iTD1_D, // TV Decoder1 Data bus 8 bits
160 input iTD1_HS, // TV Decoder1 H_SYNC
161 input iTD1_VS, // TV Decoder1 V_SYNC
162 output oTD1_RESET_N, // TV Decoder1 Reset
163 input iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
164 input [7:0] iTD2_D, // TV Decoder2 Data bus 8 bits
165 input iTD2_HS, // TV Decoder2 H_SYNC
166 input iTD2_VS, // TV Decoder2 V_SYNC
167 output oTD2_RESET_N, // TV Decoder2 Reset
168 //////////////////////////////// GPIO ////////////////////////////////
169 inout [31:0] GPIO_0, // GPIO Connection 0 I/O
170 input GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
171 input GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
172 output GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
173 output GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
174 inout [31:0] GPIO_1, // GPIO Connection 1 I/O
175 input GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
176 input GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
177 output GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
178 output GPIO_CLKOUT_P1 // PIO Connection 1 Clock Output 1
179 );
180
181 // All inout port turn to tri-state
182 assign SD_DAT = 1'bz;
183 assign GPIO_0 = 32'hzzzzzzzzz;
184 assign GPIO_1 = 32'hzzzzzzzzz;
185 assign AUD_ADCLRCK = 1'bz;
186
187 // Turn On TV Decoder
188 assign oTD1_RESET_N = 1'bz;
189 assign oTD2_RESET_N = 1'bz;
190
191 // Flash
192 assign FL_RST_N = 1'b1;
193
194 // 16*2 LCD Module
195 assign oLCD_ON = 1'b1; // LCD ON
196 assign oLCD_BLON = 1'b1; // LCD Back Light
197
198 // Disable USB speed select
199 assign OTG_FSPEED = 1'bz;
200 assign OTG_LSPEED = 1'bz;
201
202 // FLASH
203 wire FLASH_16BIT_IP_A0;
204 assign oFLASH_BYTE_N = 1'b1; // FLASH Byte/Word Mode Configuration
205 assign oFLASH_RST_N = 1'b1; // FLASH Reset
206 assign oFLASH_WP_N = 1'b1; // FLASH Write Protect /Programming Acceleration
207
208 // SSRAM
209 wire [1:0] SRAM_DUMMY_ADDR; // used to ignore the A0/A1 pin from Cypress SSRAM IP core
210 assign oSRAM_ADSP_N = 1'b1; // SRAM Processor Address Status
211 assign oSRAM_ADV_N = 1'b1; // SRAM Burst Address Advance
212 assign oSRAM_CE2 = ~oSRAM_CE1_N; // SRAM Chip Enable
213 assign oSRAM_CE3_N = oSRAM_CE1_N; // SRAM Chip Enable
214 assign oSRAM_GW_N = 1'b1; // SRAM Global Write Enable
215 assign oSRAM_CLK = oDRAM0_CLK;
216
217 // SDRAM
218 // the sdram is shahred with rtl and nios
219 assign oDRAM1_CLK = oDRAM0_CLK;
220
221 // USB
222 assign OTG_FSPEED = 1'bz; // USB Full Speed, 0 = Enable, Z = Disable
223 assign OTG_LSPEED = 1'bz; // USB Low Speed, 0 = Enable, Z = Disable
224
225 // Clock 25MHz
226 reg iCLK_25;
227
228 always@(posedge iCLK_50)
229 iCLK_25 <= ~iCLK_25;
230
231 // NIOS CPU
232 wire CPU_CLK;
233 wire CPU_RESET_N;
234
235 Reset_Delay delay0 (
236 .iRST(iKEY[0]),
237 .iCLK(iCLK_50),
238 .oRESET(CPU_RESET_N)
239 );
240
241 // NIOS II system
242 nios_ii nios_ii0 (
243 // 1) global signals:
244 .clk_50(iCLK_50),
245 .pll_c0_system(CPU_CLK),
246 .pll_c1_memory(oDRAM0_CLK),
247 .pll_c2_audio(oAUD_XCK),
248 .reset_n(CPU_RESET_N),
249 .clk_25(iCLK_25),
250 // the_DM9000A_IF_0
251 .avs_s1_export_ENET_CLK_from_the_DM9000A(oENET_CLK),
252 .avs_s1_export_ENET_CMD_from_the_DM9000A(oENET_CMD),
253 .avs_s1_export_ENET_CS_N_from_the_DM9000A(oENET_CS_N),
254 .avs_s1_export_ENET_DATA_to_and_from_the_DM9000A(ENET_D),
255 .avs_s1_export_ENET_INT_to_the_DM9000A(iENET_INT),
256 .avs_s1_export_ENET_RD_N_from_the_DM9000A(oENET_IOR_N),
257 .avs_s1_export_ENET_RST_N_from_the_DM9000A(oENET_RESET_N),
258 .avs_s1_export_ENET_WR_N_from_the_DM9000A(oENET_IOW_N),
259 // the_ISP1362
260 .avs_hc_export_OTG_ADDR_from_the_ISP1362(oOTG_A),
261 .avs_hc_export_OTG_CS_N_from_the_ISP1362(oOTG_CS_N),
262 .avs_hc_export_OTG_DATA_to_and_from_the_ISP1362(OTG_D),
263 .avs_hc_export_OTG_INT0_to_the_ISP1362(iOTG_INT0),
264 .avs_hc_export_OTG_RD_N_from_the_ISP1362(oOTG_OE_N),
265 .avs_hc_export_OTG_RST_N_from_the_ISP1362(oOTG_RESET_N),
266 .avs_hc_export_OTG_WR_N_from_the_ISP1362(oOTG_WE_N),
267 .avs_dc_export_OTG_INT1_to_the_ISP1362(iOTG_INT1),
268 // the_audio
269 .avs_s1_export_BCLK_to_the_AUDIO(AUD_BCLK),
270 .avs_s1_export_DACLRC_to_the_AUDIO(AUD_DACLRCK),
271 .avs_s1_export_DACDAT_from_the_AUDIO(oAUD_DACDAT),
272 .avs_s1_export_ADCLRC_to_the_AUDIO(AUD_ADCLRCK),
273 .avs_s1_export_ADCDAT_to_the_AUDIO(iAUD_ADCDAT),
274 // the_i2c_sclk
275 .out_port_from_the_i2c_sclk(oI2C_SCLK),
276 // the_i2c_sdat
277 .bidir_port_to_and_from_the_i2c_sdat(I2C_SDAT),
278 // the_lcd
279 .LCD_E_from_the_lcd(oLCD_EN),
280 .LCD_RS_from_the_lcd(oLCD_RS),
281 .LCD_RW_from_the_lcd(oLCD_RW),
282 .LCD_data_to_and_from_the_lcd(LCD_D),
283 // the_pio_button
284 .in_port_to_the_pio_button(iKEY),
285 // the_pio_green_led
286 .out_port_from_the_pio_green_led(oLEDG),
287 // the_pio_red_led
288 .out_port_from_the_pio_red_led(oLEDR),
289 // the_seg7
290 .avs_s1_export_seg7_from_the_SEG7({oHEX7_DP, oHEX7_D, oHEX6_DP, oHEX6_D, oHEX5_DP,
291 oHEX5_D, oHEX4_DP,oHEX4_D, oHEX3_DP, oHEX3_D, oHEX2_DP, oHEX2_D, oHEX1_DP, oHEX1_D,
292 oHEX0_DP, oHEX0_D}),
293 // the_pio_switch
294 .in_port_to_the_pio_switch(iSW),
295 // the_sd_clk
296 .out_port_from_the_sd_clk(oSD_CLK),
297 // the_sd_cmd
298 .bidir_port_to_and_from_the_sd_cmd(SD_CMD),
299 // the_sd_dat
300 .bidir_port_to_and_from_the_sd_dat(SD_DAT),
301 // the_sd_dat3
302 .bidir_port_to_and_from_the_sd_dat3(SD_DAT3),
303 // the_sdram (u1)
304 .zs_addr_from_the_sdram_u1(oDRAM0_A),
305 .zs_ba_from_the_sdram_u1(oDRAM0_BA),
306 .zs_cas_n_from_the_sdram_u1(oDRAM0_CAS_N),
307 .zs_cke_from_the_sdram_u1(oDRAM0_CKE),
308 .zs_cs_n_from_the_sdram_u1(oDRAM0_CS_N),
309 .zs_dq_to_and_from_the_sdram_u1(DRAM_DQ[15:0]),
310 .zs_dqm_from_the_sdram_u1({oDRAM0_UDQM1,oDRAM0_LDQM0}),
311 .zs_ras_n_from_the_sdram_u1(oDRAM0_RAS_N),
312 .zs_we_n_from_the_sdram_u1(oDRAM0_WE_N),
313 // the_sdram (u2)
314 .zs_addr_from_the_sdram_u2(oDRAM1_A),
315 .zs_ba_from_the_sdram_u2(oDRAM1_BA),
316 .zs_cas_n_from_the_sdram_u2(oDRAM1_CAS_N),
317 .zs_cke_from_the_sdram_u2(oDRAM1_CKE),
318 .zs_cs_n_from_the_sdram_u2(oDRAM1_CS_N),
319 .zs_dq_to_and_from_the_sdram_u2(DRAM_DQ[31:16]),
320 .zs_dqm_from_the_sdram_u2({oDRAM1_UDQM1,oDRAM1_LDQM0}),
321 .zs_ras_n_from_the_sdram_u2(oDRAM1_RAS_N),
322 .zs_we_n_from_the_sdram_u2(oDRAM1_WE_N),
323 // the_tristate_bridge_avalon_slave (flash)
324 .address_to_the_cfi_flash({oFLASH_A[21:0],FLASH_16BIT_IP_A0}),
325 .data_to_and_from_the_cfi_flash({FLASH_DQ15_AM1,FLASH_DQ}),
326 .read_n_to_the_cfi_flash(oFLASH_OE_N),
327 .select_n_to_the_cfi_flash(oFLASH_CE_N),
328 .write_n_to_the_cfi_flash(oFLASH_WE_N),
329 // the_tristate_bridge_1_avalon_slave (ssram)
330 .address_to_the_ssram({oSRAM_A[17:0],SRAM_DUMMY_ADDR}),
331 .adsc_n_to_the_ssram(oSRAM_ADSC_N),
332 .bw_n_to_the_ssram(oSRAM_BE_N),
333 .bwe_n_to_the_ssram(oSRAM_WE_N),
334 .chipenable1_n_to_the_ssram(oSRAM_CE1_N),
335 .data_to_and_from_the_ssram((SRAM_DQ)),
336 .outputenable_n_to_the_ssram(oSRAM_OE_N),
337 // the_uart
338 .cts_n_to_the_uart(oUART_CTS),
339 .rts_n_from_the_uart(iUART_RTS),
340 .rxd_to_the_uart(iUART_RXD),
341 .txd_from_the_uart(oUART_TXD),
342 );
343
344 endmodule
完整程式碼下載
DE2_70_NIOS_10.7z
Conclusion
至於很多人很關心的Nios II能用的CMOS Controller，也就是讓Nios II的C除了能控制free run與capture外，還要能抓到CMOS所capture的影像，進而用C做演算法處理。我今天已經寫出這個component，在DE2-70 + TRDB-D5M + XVGA測試成功，目前正在測試DE2-70 + TRDB-D5M + LTM，若也能正常，我就會放出這個TRDB-D5M的Nios II IP，畢竟無法在Nios II上完整控制CMOS，一直是大家長久的遺憾，希望能趕快寫出來。
See Also
(原創) 如何在Nios II讀出CMOS放在SDRAM中的影像? (SOC) (SOPC Builder) (Nios II) (DE2-70) (TRDB-D5M)
(原創) DE2_NIOS_Lite 1.0 (SOC) (Nios II) (SOPC Builder) (DE2)
(原創) DE2_NIOS_Lite 1.1 (SOC) (Nios II) (SOPC Builder) (μC/OS-II) (DE2)
(原創) DE2_NIOS_Lite 1.2 (SOC) (Nios II) (SOPC Builder) (DE2)
(原創) 如何以32 bit的方式存取SDRAM? (SOC) (Nios II) (SOPC Builder) (DE2-70)
