(原創) DE2_70_D5M_XVGA 1.0 (SOC) (DE2-70)
在DE2-70的範例中，一直找不到DE2-70 + 500萬像素CMOS + VGA的範例，只好自己弄一個。
Abstract
在DE2-70的範例中，一直找不到DE2-70 + 500萬像素CMOS + VGA的範例，只好自己弄一個。
Introduction
使用環境：Quartus II 7.2 SP3 + DE2-70 (Cyclone II EP2C70F896C6N)
在DE2平台上，DE2 + 130萬像素CMOS + 640 x 480 VGA的DE2_CCD範例，一直是大家研究電腦視覺的經典範例，到了更強大的DE2-70後，或許因為DE2-70 + 500萬像素CMOS + 800 x 480 LTM三合一套件的關係，原廠CD就找不到對等於DE2_CCD的範例了。在TRDB_D5M_CD_v1.0.zip 中的\TRDB_D5M_CD_v1.0\DE2_70_CAMERA\HW\DE2_70_CAMERA\ 中勉強找到較類似的範例：DE2-70 + 500萬像素CMOS + 1280 x 1024 XVGA。這個範例充分的發揮DE2-70兩顆32MB SDRAM的特性，不像DE2因為只有一顆8MB SDRAM，所以必須靠2 read與2 write來share SDRAM頻寬，此範例將GB寫在第一顆SDRAM，GR寫在第二顆SDRAM，這樣就不用再share同一顆SDRAM的頻寬，並且SDRAM的clock達到166MHz(DE2為125MHz)，這樣有什麼好處呢?這使的外接VGA的解析度可以高達XVGA的1280 x 1024 x 60MHz(DE2_CCD範例為640 x 480 x 60MHz)，整個VGA的control clock高達108MHz(參見(筆記) D-Sub VGA timing table (SOC) (DE2) (DE2-70))(DE2的VGA control clock為25MHz)，如此再也不會糟蹋500萬像素CMOS的2592 x 1944的實力。
不過很可惜這個範例還包含了Nios II與SOPC，對於想弄純硬體電腦視覺的人略顯多餘，我特別將Nios II與SOPC部分拔除，只留下純硬體部分，若你想在DE2-70 + 500萬像素CMOS + 1280 x 1024 XVGA的平台加上純硬體的電腦視覺前處理與後處理演算法，可以用我改過的這個版本當作DE2-70的DE2_CCD繼續開發。
DE2_70_D5M_XVGA.v / Verilog
1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : DE2_70_D5M_XVGA.v
5 Compiler : Quartus II 7.2 SP3
6 Description : Demo how to use TRDB-D5M with 1280 x 1024 XVGA
7 Release : 08/22/2008 1.0
8 */
9
10 module DE2_70_D5M_XVGA (
11 //////////////////////// Clock Input ////////////////////////
12 input iCLK_28, // 28.63636 MHz
13 input iCLK_50, // 50 MHz
14 input iCLK_50_2, // 50 MHz
15 input iCLK_50_3, // 50 MHz
16 input iCLK_50_4, // 50 MHz
17 input iEXT_CLOCK, // External Clock
18 //////////////////////// Push Button ////////////////////////
19 input [3:0] iKEY, // Pushbutton[3:0]
20 //////////////////////// DPDT Switch ////////////////////////
21 input [17:0] iSW, // Toggle Switch[17:0]
22 //////////////////////// 7-SEG Dispaly ////////////////////////
23 output [6:0] oHEX0_D, // Seven Segment Digit 0
24 output oHEX0_DP, // Seven Segment Digit 0 decimal point
25 output [6:0] oHEX1_D, // Seven Segment Digit 1
26 output oHEX1_DP, // Seven Segment Digit 1 decimal point
27 output [6:0] oHEX2_D, // Seven Segment Digit 2
28 output oHEX2_DP, // Seven Segment Digit 2 decimal point
29 output [6:0] oHEX3_D, // Seven Segment Digit 3
30 output oHEX3_DP, // Seven Segment Digit 3 decimal point
31 output [6:0] oHEX4_D, // Seven Segment Digit 4
32 output oHEX4_DP, // Seven Segment Digit 4 decimal point
33 output [6:0] oHEX5_D, // Seven Segment Digit 5
34 output oHEX5_DP, // Seven Segment Digit 5 decimal point
35 output [6:0] oHEX6_D, // Seven Segment Digit 6
36 output oHEX6_DP, // Seven Segment Digit 6 decimal point
37 output [6:0] oHEX7_D, // Seven Segment Digit 7
38 output oHEX7_DP, // Seven Segment Digit 7 decimal point
39 //////////////////////////// LED ////////////////////////////
40 output [8:0] oLEDG, // LED Green[8:0]
41 output [17:0] oLEDR, // LED Red[17:0]
42 //////////////////////////// UART ////////////////////////////
43 output oUART_TXD, // UART Transmitter
44 input iUART_RXD, // UART Receiver
45 output oUART_CTS, // UART Clear To Send
46 input iUART_RTS, // UART Requst To Send
47 //////////////////////////// IRDA ////////////////////////////
48 output oIRDA_TXD, // IRDA Transmitter
49 input iIRDA_RXD, // IRDA Receiver
50 /////////////////////// SDRAM Interface ////////////////////////
51 inout [31:0] DRAM_DQ, // SDRAM Data bus 32 Bits
52 output [12:0] oDRAM0_A, // SDRAM0 Address bus 13 Bits
53 output [12:0] oDRAM1_A, // SDRAM1 Address bus 13 Bits
54 output oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
55 output oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
56 output oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
57 output oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
58 output oDRAM0_WE_N, // SDRAM0 Write Enable
59 output oDRAM1_WE_N, // SDRAM1 Write Enable
60 output oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
61 output oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
62 output oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
63 output oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
64 output oDRAM0_CS_N, // SDRAM0 Chip Select
65 output oDRAM1_CS_N, // SDRAM1 Chip Select
66 output [1:0] oDRAM0_BA, // SDRAM0 Bank Address
67 output [1:0] oDRAM1_BA, // SDRAM1 Bank Address
68 output oDRAM0_CLK, // SDRAM0 Clock
69 output oDRAM1_CLK, // SDRAM1 Clock
70 output oDRAM0_CKE, // SDRAM0 Clock Enable
71 output oDRAM1_CKE, // SDRAM1 Clock Enable
72 //////////////////////// Flash Interface ////////////////////////
73 inout [14:0] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
74 inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
75 output [21:0] oFLASH_A, // FLASH Address bus 26 Bits
76 output oFLASH_WE_N, // FLASH Write Enable
77 output oFLASH_RST_N, // FLASH Reset
78 output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
79 input iFLASH_RY_N, // FLASH Ready/Busy output
80 output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
81 output oFLASH_OE_N, // FLASH Output Enable
82 output oFLASH_CE_N, // FLASH Chip Enable
83 //////////////////////// SRAM Interface ////////////////////////
84 inout [31:0] SRAM_DQ, // SRAM Data Bus 32 Bits
85 inout [3:0] SRAM_DPA, // SRAM Parity Data Bus
86 output [18:0] oSRAM_A, // SRAM Address bus 21 Bits
87 output oSRAM_ADSC_N, // SRAM Controller Address Status
88 output oSRAM_ADSP_N, // SRAM Processor Address Status
89 output oSRAM_ADV_N, // SRAM Burst Address Advance
90 output [3:0] oSRAM_BE_N, // SRAM Byte Write Enable
91 output oSRAM_CE1_N, // SRAM Chip Enable
92 output oSRAM_CE2, // SRAM Chip Enable
93 output oSRAM_CE3_N, // SRAM Chip Enable
94 output oSRAM_CLK, // SRAM Clock
95 output oSRAM_GW_N, // SRAM Global Write Enable
96 output oSRAM_OE_N, // SRAM Output Enable
97 output oSRAM_WE_N, // SRAM Write Enable
98 //////////////////// ISP1362 Interface ////////////////////////
99 inout [15:0] OTG_D, // ISP1362 Data bus 16 Bits
100 output [1:0] oOTG_A, // ISP1362 Address 2 Bits
101 output oOTG_CS_N, // ISP1362 Chip Select
102 output oOTG_OE_N, // ISP1362 Read
103 output oOTG_WE_N, // ISP1362 Write
104 output oOTG_RESET_N, // ISP1362 Reset
105 inout OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
106 inout OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
107 input iOTG_INT0, // ISP1362 Interrupt 0
108 input iOTG_INT1, // ISP1362 Interrupt 1
109 input iOTG_DREQ0, // ISP1362 DMA Request 0
110 input iOTG_DREQ1, // ISP1362 DMA Request 1
111 output oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
112 output oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
113 //////////////////// LCD Module 16X2 ////////////////////////////
114 inout [7:0] LCD_D, // LCD Data bus 8 bits
115 output oLCD_ON, // LCD Power ON/OFF
116 output oLCD_BLON, // LCD Back Light ON/OFF
117 output oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
118 output oLCD_EN, // LCD Enable
119 output oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
120 //////////////////// SD Card Interface ////////////////////////
121 inout SD_DAT, // SD Card Data
122 inout SD_DAT3, // SD Card Data 3
123 inout SD_CMD, // SD Card Command Signal
124 output oSD_CLK, // SD Card Clock
125 //////////////////////// I2C ////////////////////////////////
126 inout I2C_SDAT, // I2C Data
127 output oI2C_SCLK, // I2C Clock
128 //////////////////////// PS2 ////////////////////////////////
129 inout PS2_KBDAT, // PS2 Keyboard Data
130 inout PS2_KBCLK, // PS2 Keyboard Clock
131 inout PS2_MSDAT, // PS2 Mouse Data
132 inout PS2_MSCLK, // PS2 Mouse Clock
133 //////////////////////// VGA ////////////////////////////
134 output oVGA_CLOCK, // VGA Clock
135 output oVGA_HS, // VGA H_SYNC
136 output oVGA_VS, // VGA V_SYNC
137 output oVGA_BLANK_N, // VGA BLANK
138 output oVGA_SYNC_N, // VGA SYNC
139 output [9:0] oVGA_R, // VGA Red[9:0]
140 output [9:0] oVGA_G, // VGA Green[9:0]
141 output [9:0] oVGA_B, // VGA Blue[9:0]
142 //////////////// Ethernet Interface ////////////////////////////
143 inout [15:0] ENET_D, // DM9000A DATA bus 16Bits
144 output oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
145 output oENET_CS_N, // DM9000A Chip Select
146 output oENET_IOW_N, // DM9000A Write
147 output oENET_IOR_N, // DM9000A Read
148 output oENET_RESET_N, // DM9000A Reset
149 input iENET_INT, // DM9000A Interrupt
150 output oENET_CLK, // DM9000A Clock 25 MHz
151 //////////////////// Audio CODEC ////////////////////////////
152 inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
153 input iAUD_ADCDAT, // Audio CODEC ADC Data
154 inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
155 output oAUD_DACDAT, // Audio CODEC DAC Data
156 inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
157 output oAUD_XCK, // Audio CODEC Chip Clock
158 //////////////////// TV Devoder ////////////////////////////
159 input iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
160 input [7:0] iTD1_D, // TV Decoder1 Data bus 8 bits
161 input iTD1_HS, // TV Decoder1 H_SYNC
162 input iTD1_VS, // TV Decoder1 V_SYNC
163 output oTD1_RESET_N, // TV Decoder1 Reset
164 input iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
165 input [7:0] iTD2_D, // TV Decoder2 Data bus 8 bits
166 input iTD2_HS, // TV Decoder2 H_SYNC
167 input iTD2_VS, // TV Decoder2 V_SYNC
168 output oTD2_RESET_N, // TV Decoder2 Reset
169 //////////////////////// GPIO ////////////////////////////////
170 inout [31:0] GPIO_0, // GPIO Connection 0 I/O
171 input GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
172 input GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
173 inout GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
174 inout GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
175 inout [31:0] GPIO_1, // GPIO Connection 1 I/O
176 input GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
177 input GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
178 inout GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
179 inout GPIO_CLKOUT_P1 // GPIO Connection 1 Clock Output 1
180 );
181
182 // CCD
183 wire [11:0] CCD_DATA;
184 wire CCD_SDAT;
185 wire CCD_SCLK;
186 wire CCD_FLASH;
187 wire CCD_FVAL;
188 wire CCD_LVAL;
189 wire CCD_PIXCLK;
190 wire CCD_MCLK; // CCD Master Clock
191
192 wire [15:0] Read_DATA1;
193 wire [15:0] Read_DATA2;
194 wire VGA_CTRL_CLK;
195 wire [11:0] mCCD_DATA;
196 wire mCCD_DVAL;
197 wire mCCD_DVAL_d;
198 wire [15:0] X_Cont;
199 wire [15:0] Y_Cont;
200 wire [9:0] X_ADDR;
201 wire [31:0] Frame_Cont;
202 wire DLY_RST_0;
203 wire DLY_RST_1;
204 wire DLY_RST_2;
205 wire Read;
206 reg [11:0] rCCD_DATA;
207 reg rCCD_LVAL;
208 reg rCCD_FVAL;
209 wire [11:0] sCCD_R;
210 wire [11:0] sCCD_G;
211 wire [11:0] sCCD_B;
212 wire sCCD_DVAL;
213 reg [1:0] rClk;
214 wire sdram_ctrl_clk;
215
216 assign CCD_DATA[0] = GPIO_1[11];
217 assign CCD_DATA[1] = GPIO_1[10];
218 assign CCD_DATA[2] = GPIO_1[9];
219 assign CCD_DATA[3] = GPIO_1[8];
220 assign CCD_DATA[4] = GPIO_1[7];
221 assign CCD_DATA[5] = GPIO_1[6];
222 assign CCD_DATA[6] = GPIO_1[5];
223 assign CCD_DATA[7] = GPIO_1[4];
224 assign CCD_DATA[8] = GPIO_1[3];
225 assign CCD_DATA[9] = GPIO_1[2];
226 assign CCD_DATA[10] = GPIO_1[1];
227 assign CCD_DATA[11] = GPIO_1[0];
228
229 assign GPIO_CLKOUT_N1 = CCD_MCLK;
230 assign CCD_FVAL = GPIO_1[18];
231 assign CCD_LVAL = GPIO_1[17];
232 assign CCD_PIXCLK = GPIO_CLKIN_N1;
233
234 assign GPIO_1[15] = 1'b1; // tRIGGER
235 assign GPIO_1[14] = DLY_RST_1;
236
237 assign oLEDR = iSW;
238
239 assign oTD1_RESET_N = 1'b1;
240 assign oVGA_CLOCK =~VGA_CTRL_CLK;
241 assign CCD_MCLK = rClk[0];
242
243 vga_pll vga_pll0 (
244 .areset(!DLY_RST_0),
245 .inclk0(iTD1_CLK27),
246 .c0(VGA_CTRL_CLK)
247 );
248
249 VGA_Controller vga0 (
250 // Host Side
251 .oRequest(Read),
252 .iRed(Read_DATA2[9:0]),
253 .iGreen({Read_DATA1[14:10], Read_DATA2[14:10]}),
254 .iBlue(Read_DATA1[9:0]),
255 // VGA Side
256 .oVGA_R(oVGA_R),
257 .oVGA_G(oVGA_G),
258 .oVGA_B(oVGA_B),
259 .oVGA_H_SYNC(oVGA_HS),
260 .oVGA_V_SYNC(oVGA_VS),
261 .oVGA_SYNC(oVGA_SYNC_N),
262 .oVGA_BLANK(oVGA_BLANK_N),
263 // Control Signal
264 .iCLK(VGA_CTRL_CLK),
265 .iRST_N(DLY_RST_2),
266 .iZOOM_MODE_SW(iSW[16])
267 );
268
269 Reset_Delay reset0 (
270 .iCLK(iCLK_50),
271 .iRST(iKEY[0]),
272 .oRST_0(DLY_RST_0),
273 .oRST_1(DLY_RST_1),
274 .oRST_2(DLY_RST_2)
275 );
276
277 CCD_Capture capture0 (
278 .oDATA(mCCD_DATA),
279 .oDVAL(mCCD_DVAL),
280 .oX_Cont(X_Cont),
281 .oY_Cont(Y_Cont),
282 .oFrame_Cont(Frame_Cont),
283 .iDATA(rCCD_DATA),
284 .iFVAL(rCCD_FVAL),
285 .iLVAL(rCCD_LVAL),
286 .iSTART(!iKEY[3]),
287 .iEND(!iKEY[2]),
288 .iCLK(CCD_PIXCLK),
289 .iRST(DLY_RST_2)
290 );
291
292 RAW2RGB rgb0 (
293 .iCLK(CCD_PIXCLK),
294 .iRST_n(DLY_RST_1),
295 .iData(mCCD_DATA),
296 .iDval(mCCD_DVAL),
297 .oRed(sCCD_R),
298 .oGreen(sCCD_G),
299 .oBlue(sCCD_B),
300 .oDval(sCCD_DVAL),
301 .iZoom(iSW[17:16]),
302 .iX_Cont(X_Cont),
303 .iY_Cont(Y_Cont)
304 );
305
306 SEG7_LUT_8 seg70 (
307 .oSEG0(oHEX0_D),
308 .oSEG1(oHEX1_D),
309 .oSEG2(oHEX2_D),
310 .oSEG3(oHEX3_D),
311 .oSEG4(oHEX4_D),
312 .oSEG5(oHEX5_D),
313 .oSEG6(oHEX6_D),
314 .oSEG7(oHEX7_D),
315 .iDIG(Frame_Cont[31:0])
316 );
317
318 sdram_pll sdram_pll0 (
319 .inclk0(iCLK_50),
320 .c0(sdram_ctrl_clk),
321 .c1(oDRAM0_CLK),
322 .c2(oDRAM1_CLK)
323 );
324
325 Sdram_Control_4Port sdram0 (
326 // HOST Side
327 .REF_CLK(iCLK_50),
328 .RESET_N(1'b1),
329 .CLK(sdram_ctrl_clk),
330 // FIFO Write Side 1
331 .WR1_DATA({sCCD_G[11:7], sCCD_B[11:2]}),
332 .WR1(sCCD_DVAL),
333 .WR1_ADDR(0),
334 .WR1_MAX_ADDR(1280*1024),
335 .WR1_LENGTH(9'h100),
336 .WR1_LOAD(!DLY_RST_0),
337 .WR1_CLK(CCD_PIXCLK),
338 // FIFO Read Side 1
339 .RD1_DATA(Read_DATA1),
340 .RD1(Read),
341 .RD1_ADDR(0),
342 .RD1_MAX_ADDR(1280*1024),
343 .RD1_LENGTH(9'h100),
344 .RD1_LOAD(!DLY_RST_0),
345 .RD1_CLK(VGA_CTRL_CLK),
346 // SDRAM Side
347 .SA(oDRAM0_A[11:0]),
348 .BA(oDRAM0_BA),
349 .CS_N(oDRAM0_CS_N),
350 .CKE(oDRAM0_CKE),
351 .RAS_N(oDRAM0_RAS_N),
352 .CAS_N(oDRAM0_CAS_N),
353 .WE_N(oDRAM0_WE_N),
354 .DQ(DRAM_DQ[15:0]),
355 .DQM({oDRAM0_UDQM1,oDRAM0_LDQM0})
356 );
357
358 Sdram_Control_4Port sdram1 (
359 // HOST Side
360 .REF_CLK(iCLK_50),
361 .RESET_N(1'b1),
362 .CLK(sdram_ctrl_clk),
363 // FIFO Write Side 1
364 .WR1_DATA({sCCD_G[6:2], sCCD_R[11:2]}),
365 .WR1(sCCD_DVAL),
366 .WR1_ADDR(0),
367 .WR1_MAX_ADDR(1280*1024),
368 .WR1_LENGTH(9'h100),
369 .WR1_LOAD(!DLY_RST_0),
370 .WR1_CLK(CCD_PIXCLK),
371 // FIFO Read Side 1
372 .RD1_DATA(Read_DATA2),
373 .RD1(Read),
374 .RD1_ADDR(0),
375 .RD1_MAX_ADDR(1280*1024),
376 .RD1_LENGTH(9'h100),
377 .RD1_LOAD(!DLY_RST_0),
378 .RD1_CLK(VGA_CTRL_CLK),
379 // SDRAM Side
380 .SA(oDRAM1_A[11:0]),
381 .BA(oDRAM1_BA),
382 .CS_N(oDRAM1_CS_N),
383 .CKE(oDRAM1_CKE),
384 .RAS_N(oDRAM1_RAS_N),
385 .CAS_N(oDRAM1_CAS_N),
386 .WE_N(oDRAM1_WE_N),
387 .DQ(DRAM_DQ[31:16]),
388 .DQM({oDRAM1_UDQM1,oDRAM1_LDQM0})
389 );
390
391 I2C_CCD_Config i2c0 (
392 // Host Side
393 .iCLK(iCLK_50),
394 .iRST_N(DLY_RST_2),
395 .iZOOM_MODE_SW(iSW[16]),
396 .iEXPOSURE_ADJ(iKEY[1]),
397 .iEXPOSURE_DEC_p(iSW[0]),
398 // I2C Side
399 .I2C_SCLK(GPIO_1[20]),
400 .I2C_SDAT(GPIO_1[19])
401 );
402
403 always@(posedge iCLK_50)
404 rClk <= rClk+1;
405
406 always@(posedge CCD_PIXCLK) begin
407 rCCD_DATA <= CCD_DATA;
408 rCCD_LVAL <= CCD_LVAL;
409 rCCD_FVAL <= CCD_FVAL;
410 end
411
412 endmodule
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : DE2_70_D5M_XVGA.v
5 Compiler : Quartus II 7.2 SP3
6 Description : Demo how to use TRDB-D5M with 1280 x 1024 XVGA
7 Release : 08/22/2008 1.0
8 */
9
10 module DE2_70_D5M_XVGA (
11 //////////////////////// Clock Input ////////////////////////
12 input iCLK_28, // 28.63636 MHz
13 input iCLK_50, // 50 MHz
14 input iCLK_50_2, // 50 MHz
15 input iCLK_50_3, // 50 MHz
16 input iCLK_50_4, // 50 MHz
17 input iEXT_CLOCK, // External Clock
18 //////////////////////// Push Button ////////////////////////
19 input [3:0] iKEY, // Pushbutton[3:0]
20 //////////////////////// DPDT Switch ////////////////////////
21 input [17:0] iSW, // Toggle Switch[17:0]
22 //////////////////////// 7-SEG Dispaly ////////////////////////
23 output [6:0] oHEX0_D, // Seven Segment Digit 0
24 output oHEX0_DP, // Seven Segment Digit 0 decimal point
25 output [6:0] oHEX1_D, // Seven Segment Digit 1
26 output oHEX1_DP, // Seven Segment Digit 1 decimal point
27 output [6:0] oHEX2_D, // Seven Segment Digit 2
28 output oHEX2_DP, // Seven Segment Digit 2 decimal point
29 output [6:0] oHEX3_D, // Seven Segment Digit 3
30 output oHEX3_DP, // Seven Segment Digit 3 decimal point
31 output [6:0] oHEX4_D, // Seven Segment Digit 4
32 output oHEX4_DP, // Seven Segment Digit 4 decimal point
33 output [6:0] oHEX5_D, // Seven Segment Digit 5
34 output oHEX5_DP, // Seven Segment Digit 5 decimal point
35 output [6:0] oHEX6_D, // Seven Segment Digit 6
36 output oHEX6_DP, // Seven Segment Digit 6 decimal point
37 output [6:0] oHEX7_D, // Seven Segment Digit 7
38 output oHEX7_DP, // Seven Segment Digit 7 decimal point
39 //////////////////////////// LED ////////////////////////////
40 output [8:0] oLEDG, // LED Green[8:0]
41 output [17:0] oLEDR, // LED Red[17:0]
42 //////////////////////////// UART ////////////////////////////
43 output oUART_TXD, // UART Transmitter
44 input iUART_RXD, // UART Receiver
45 output oUART_CTS, // UART Clear To Send
46 input iUART_RTS, // UART Requst To Send
47 //////////////////////////// IRDA ////////////////////////////
48 output oIRDA_TXD, // IRDA Transmitter
49 input iIRDA_RXD, // IRDA Receiver
50 /////////////////////// SDRAM Interface ////////////////////////
51 inout [31:0] DRAM_DQ, // SDRAM Data bus 32 Bits
52 output [12:0] oDRAM0_A, // SDRAM0 Address bus 13 Bits
53 output [12:0] oDRAM1_A, // SDRAM1 Address bus 13 Bits
54 output oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
55 output oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
56 output oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
57 output oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
58 output oDRAM0_WE_N, // SDRAM0 Write Enable
59 output oDRAM1_WE_N, // SDRAM1 Write Enable
60 output oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
61 output oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
62 output oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
63 output oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
64 output oDRAM0_CS_N, // SDRAM0 Chip Select
65 output oDRAM1_CS_N, // SDRAM1 Chip Select
66 output [1:0] oDRAM0_BA, // SDRAM0 Bank Address
67 output [1:0] oDRAM1_BA, // SDRAM1 Bank Address
68 output oDRAM0_CLK, // SDRAM0 Clock
69 output oDRAM1_CLK, // SDRAM1 Clock
70 output oDRAM0_CKE, // SDRAM0 Clock Enable
71 output oDRAM1_CKE, // SDRAM1 Clock Enable
72 //////////////////////// Flash Interface ////////////////////////
73 inout [14:0] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
74 inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
75 output [21:0] oFLASH_A, // FLASH Address bus 26 Bits
76 output oFLASH_WE_N, // FLASH Write Enable
77 output oFLASH_RST_N, // FLASH Reset
78 output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
79 input iFLASH_RY_N, // FLASH Ready/Busy output
80 output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
81 output oFLASH_OE_N, // FLASH Output Enable
82 output oFLASH_CE_N, // FLASH Chip Enable
83 //////////////////////// SRAM Interface ////////////////////////
84 inout [31:0] SRAM_DQ, // SRAM Data Bus 32 Bits
85 inout [3:0] SRAM_DPA, // SRAM Parity Data Bus
86 output [18:0] oSRAM_A, // SRAM Address bus 21 Bits
87 output oSRAM_ADSC_N, // SRAM Controller Address Status
88 output oSRAM_ADSP_N, // SRAM Processor Address Status
89 output oSRAM_ADV_N, // SRAM Burst Address Advance
90 output [3:0] oSRAM_BE_N, // SRAM Byte Write Enable
91 output oSRAM_CE1_N, // SRAM Chip Enable
92 output oSRAM_CE2, // SRAM Chip Enable
93 output oSRAM_CE3_N, // SRAM Chip Enable
94 output oSRAM_CLK, // SRAM Clock
95 output oSRAM_GW_N, // SRAM Global Write Enable
96 output oSRAM_OE_N, // SRAM Output Enable
97 output oSRAM_WE_N, // SRAM Write Enable
98 //////////////////// ISP1362 Interface ////////////////////////
99 inout [15:0] OTG_D, // ISP1362 Data bus 16 Bits
100 output [1:0] oOTG_A, // ISP1362 Address 2 Bits
101 output oOTG_CS_N, // ISP1362 Chip Select
102 output oOTG_OE_N, // ISP1362 Read
103 output oOTG_WE_N, // ISP1362 Write
104 output oOTG_RESET_N, // ISP1362 Reset
105 inout OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
106 inout OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
107 input iOTG_INT0, // ISP1362 Interrupt 0
108 input iOTG_INT1, // ISP1362 Interrupt 1
109 input iOTG_DREQ0, // ISP1362 DMA Request 0
110 input iOTG_DREQ1, // ISP1362 DMA Request 1
111 output oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
112 output oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
113 //////////////////// LCD Module 16X2 ////////////////////////////
114 inout [7:0] LCD_D, // LCD Data bus 8 bits
115 output oLCD_ON, // LCD Power ON/OFF
116 output oLCD_BLON, // LCD Back Light ON/OFF
117 output oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
118 output oLCD_EN, // LCD Enable
119 output oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
120 //////////////////// SD Card Interface ////////////////////////
121 inout SD_DAT, // SD Card Data
122 inout SD_DAT3, // SD Card Data 3
123 inout SD_CMD, // SD Card Command Signal
124 output oSD_CLK, // SD Card Clock
125 //////////////////////// I2C ////////////////////////////////
126 inout I2C_SDAT, // I2C Data
127 output oI2C_SCLK, // I2C Clock
128 //////////////////////// PS2 ////////////////////////////////
129 inout PS2_KBDAT, // PS2 Keyboard Data
130 inout PS2_KBCLK, // PS2 Keyboard Clock
131 inout PS2_MSDAT, // PS2 Mouse Data
132 inout PS2_MSCLK, // PS2 Mouse Clock
133 //////////////////////// VGA ////////////////////////////
134 output oVGA_CLOCK, // VGA Clock
135 output oVGA_HS, // VGA H_SYNC
136 output oVGA_VS, // VGA V_SYNC
137 output oVGA_BLANK_N, // VGA BLANK
138 output oVGA_SYNC_N, // VGA SYNC
139 output [9:0] oVGA_R, // VGA Red[9:0]
140 output [9:0] oVGA_G, // VGA Green[9:0]
141 output [9:0] oVGA_B, // VGA Blue[9:0]
142 //////////////// Ethernet Interface ////////////////////////////
143 inout [15:0] ENET_D, // DM9000A DATA bus 16Bits
144 output oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
145 output oENET_CS_N, // DM9000A Chip Select
146 output oENET_IOW_N, // DM9000A Write
147 output oENET_IOR_N, // DM9000A Read
148 output oENET_RESET_N, // DM9000A Reset
149 input iENET_INT, // DM9000A Interrupt
150 output oENET_CLK, // DM9000A Clock 25 MHz
151 //////////////////// Audio CODEC ////////////////////////////
152 inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
153 input iAUD_ADCDAT, // Audio CODEC ADC Data
154 inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
155 output oAUD_DACDAT, // Audio CODEC DAC Data
156 inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
157 output oAUD_XCK, // Audio CODEC Chip Clock
158 //////////////////// TV Devoder ////////////////////////////
159 input iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
160 input [7:0] iTD1_D, // TV Decoder1 Data bus 8 bits
161 input iTD1_HS, // TV Decoder1 H_SYNC
162 input iTD1_VS, // TV Decoder1 V_SYNC
163 output oTD1_RESET_N, // TV Decoder1 Reset
164 input iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
165 input [7:0] iTD2_D, // TV Decoder2 Data bus 8 bits
166 input iTD2_HS, // TV Decoder2 H_SYNC
167 input iTD2_VS, // TV Decoder2 V_SYNC
168 output oTD2_RESET_N, // TV Decoder2 Reset
169 //////////////////////// GPIO ////////////////////////////////
170 inout [31:0] GPIO_0, // GPIO Connection 0 I/O
171 input GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
172 input GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
173 inout GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
174 inout GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
175 inout [31:0] GPIO_1, // GPIO Connection 1 I/O
176 input GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
177 input GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
178 inout GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
179 inout GPIO_CLKOUT_P1 // GPIO Connection 1 Clock Output 1
180 );
181
182 // CCD
183 wire [11:0] CCD_DATA;
184 wire CCD_SDAT;
185 wire CCD_SCLK;
186 wire CCD_FLASH;
187 wire CCD_FVAL;
188 wire CCD_LVAL;
189 wire CCD_PIXCLK;
190 wire CCD_MCLK; // CCD Master Clock
191
192 wire [15:0] Read_DATA1;
193 wire [15:0] Read_DATA2;
194 wire VGA_CTRL_CLK;
195 wire [11:0] mCCD_DATA;
196 wire mCCD_DVAL;
197 wire mCCD_DVAL_d;
198 wire [15:0] X_Cont;
199 wire [15:0] Y_Cont;
200 wire [9:0] X_ADDR;
201 wire [31:0] Frame_Cont;
202 wire DLY_RST_0;
203 wire DLY_RST_1;
204 wire DLY_RST_2;
205 wire Read;
206 reg [11:0] rCCD_DATA;
207 reg rCCD_LVAL;
208 reg rCCD_FVAL;
209 wire [11:0] sCCD_R;
210 wire [11:0] sCCD_G;
211 wire [11:0] sCCD_B;
212 wire sCCD_DVAL;
213 reg [1:0] rClk;
214 wire sdram_ctrl_clk;
215
216 assign CCD_DATA[0] = GPIO_1[11];
217 assign CCD_DATA[1] = GPIO_1[10];
218 assign CCD_DATA[2] = GPIO_1[9];
219 assign CCD_DATA[3] = GPIO_1[8];
220 assign CCD_DATA[4] = GPIO_1[7];
221 assign CCD_DATA[5] = GPIO_1[6];
222 assign CCD_DATA[6] = GPIO_1[5];
223 assign CCD_DATA[7] = GPIO_1[4];
224 assign CCD_DATA[8] = GPIO_1[3];
225 assign CCD_DATA[9] = GPIO_1[2];
226 assign CCD_DATA[10] = GPIO_1[1];
227 assign CCD_DATA[11] = GPIO_1[0];
228
229 assign GPIO_CLKOUT_N1 = CCD_MCLK;
230 assign CCD_FVAL = GPIO_1[18];
231 assign CCD_LVAL = GPIO_1[17];
232 assign CCD_PIXCLK = GPIO_CLKIN_N1;
233
234 assign GPIO_1[15] = 1'b1; // tRIGGER
235 assign GPIO_1[14] = DLY_RST_1;
236
237 assign oLEDR = iSW;
238
239 assign oTD1_RESET_N = 1'b1;
240 assign oVGA_CLOCK =~VGA_CTRL_CLK;
241 assign CCD_MCLK = rClk[0];
242
243 vga_pll vga_pll0 (
244 .areset(!DLY_RST_0),
245 .inclk0(iTD1_CLK27),
246 .c0(VGA_CTRL_CLK)
247 );
248
249 VGA_Controller vga0 (
250 // Host Side
251 .oRequest(Read),
252 .iRed(Read_DATA2[9:0]),
253 .iGreen({Read_DATA1[14:10], Read_DATA2[14:10]}),
254 .iBlue(Read_DATA1[9:0]),
255 // VGA Side
256 .oVGA_R(oVGA_R),
257 .oVGA_G(oVGA_G),
258 .oVGA_B(oVGA_B),
259 .oVGA_H_SYNC(oVGA_HS),
260 .oVGA_V_SYNC(oVGA_VS),
261 .oVGA_SYNC(oVGA_SYNC_N),
262 .oVGA_BLANK(oVGA_BLANK_N),
263 // Control Signal
264 .iCLK(VGA_CTRL_CLK),
265 .iRST_N(DLY_RST_2),
266 .iZOOM_MODE_SW(iSW[16])
267 );
268
269 Reset_Delay reset0 (
270 .iCLK(iCLK_50),
271 .iRST(iKEY[0]),
272 .oRST_0(DLY_RST_0),
273 .oRST_1(DLY_RST_1),
274 .oRST_2(DLY_RST_2)
275 );
276
277 CCD_Capture capture0 (
278 .oDATA(mCCD_DATA),
279 .oDVAL(mCCD_DVAL),
280 .oX_Cont(X_Cont),
281 .oY_Cont(Y_Cont),
282 .oFrame_Cont(Frame_Cont),
283 .iDATA(rCCD_DATA),
284 .iFVAL(rCCD_FVAL),
285 .iLVAL(rCCD_LVAL),
286 .iSTART(!iKEY[3]),
287 .iEND(!iKEY[2]),
288 .iCLK(CCD_PIXCLK),
289 .iRST(DLY_RST_2)
290 );
291
292 RAW2RGB rgb0 (
293 .iCLK(CCD_PIXCLK),
294 .iRST_n(DLY_RST_1),
295 .iData(mCCD_DATA),
296 .iDval(mCCD_DVAL),
297 .oRed(sCCD_R),
298 .oGreen(sCCD_G),
299 .oBlue(sCCD_B),
300 .oDval(sCCD_DVAL),
301 .iZoom(iSW[17:16]),
302 .iX_Cont(X_Cont),
303 .iY_Cont(Y_Cont)
304 );
305
306 SEG7_LUT_8 seg70 (
307 .oSEG0(oHEX0_D),
308 .oSEG1(oHEX1_D),
309 .oSEG2(oHEX2_D),
310 .oSEG3(oHEX3_D),
311 .oSEG4(oHEX4_D),
312 .oSEG5(oHEX5_D),
313 .oSEG6(oHEX6_D),
314 .oSEG7(oHEX7_D),
315 .iDIG(Frame_Cont[31:0])
316 );
317
318 sdram_pll sdram_pll0 (
319 .inclk0(iCLK_50),
320 .c0(sdram_ctrl_clk),
321 .c1(oDRAM0_CLK),
322 .c2(oDRAM1_CLK)
323 );
324
325 Sdram_Control_4Port sdram0 (
326 // HOST Side
327 .REF_CLK(iCLK_50),
328 .RESET_N(1'b1),
329 .CLK(sdram_ctrl_clk),
330 // FIFO Write Side 1
331 .WR1_DATA({sCCD_G[11:7], sCCD_B[11:2]}),
332 .WR1(sCCD_DVAL),
333 .WR1_ADDR(0),
334 .WR1_MAX_ADDR(1280*1024),
335 .WR1_LENGTH(9'h100),
336 .WR1_LOAD(!DLY_RST_0),
337 .WR1_CLK(CCD_PIXCLK),
338 // FIFO Read Side 1
339 .RD1_DATA(Read_DATA1),
340 .RD1(Read),
341 .RD1_ADDR(0),
342 .RD1_MAX_ADDR(1280*1024),
343 .RD1_LENGTH(9'h100),
344 .RD1_LOAD(!DLY_RST_0),
345 .RD1_CLK(VGA_CTRL_CLK),
346 // SDRAM Side
347 .SA(oDRAM0_A[11:0]),
348 .BA(oDRAM0_BA),
349 .CS_N(oDRAM0_CS_N),
350 .CKE(oDRAM0_CKE),
351 .RAS_N(oDRAM0_RAS_N),
352 .CAS_N(oDRAM0_CAS_N),
353 .WE_N(oDRAM0_WE_N),
354 .DQ(DRAM_DQ[15:0]),
355 .DQM({oDRAM0_UDQM1,oDRAM0_LDQM0})
356 );
357
358 Sdram_Control_4Port sdram1 (
359 // HOST Side
360 .REF_CLK(iCLK_50),
361 .RESET_N(1'b1),
362 .CLK(sdram_ctrl_clk),
363 // FIFO Write Side 1
364 .WR1_DATA({sCCD_G[6:2], sCCD_R[11:2]}),
365 .WR1(sCCD_DVAL),
366 .WR1_ADDR(0),
367 .WR1_MAX_ADDR(1280*1024),
368 .WR1_LENGTH(9'h100),
369 .WR1_LOAD(!DLY_RST_0),
370 .WR1_CLK(CCD_PIXCLK),
371 // FIFO Read Side 1
372 .RD1_DATA(Read_DATA2),
373 .RD1(Read),
374 .RD1_ADDR(0),
375 .RD1_MAX_ADDR(1280*1024),
376 .RD1_LENGTH(9'h100),
377 .RD1_LOAD(!DLY_RST_0),
378 .RD1_CLK(VGA_CTRL_CLK),
379 // SDRAM Side
380 .SA(oDRAM1_A[11:0]),
381 .BA(oDRAM1_BA),
382 .CS_N(oDRAM1_CS_N),
383 .CKE(oDRAM1_CKE),
384 .RAS_N(oDRAM1_RAS_N),
385 .CAS_N(oDRAM1_CAS_N),
386 .WE_N(oDRAM1_WE_N),
387 .DQ(DRAM_DQ[31:16]),
388 .DQM({oDRAM1_UDQM1,oDRAM1_LDQM0})
389 );
390
391 I2C_CCD_Config i2c0 (
392 // Host Side
393 .iCLK(iCLK_50),
394 .iRST_N(DLY_RST_2),
395 .iZOOM_MODE_SW(iSW[16]),
396 .iEXPOSURE_ADJ(iKEY[1]),
397 .iEXPOSURE_DEC_p(iSW[0]),
398 // I2C Side
399 .I2C_SCLK(GPIO_1[20]),
400 .I2C_SDAT(GPIO_1[19])
401 );
402
403 always@(posedge iCLK_50)
404 rClk <= rClk+1;
405
406 always@(posedge CCD_PIXCLK) begin
407 rCCD_DATA <= CCD_DATA;
408 rCCD_LVAL <= CCD_LVAL;
409 rCCD_FVAL <= CCD_FVAL;
410 end
411
412 endmodule
325行
Sdram_Control_4Port sdram0 (
// HOST Side
.REF_CLK(iCLK_50),
.RESET_N(1'b1),
.CLK(sdram_ctrl_clk),
// FIFO Write Side 1
.WR1_DATA({sCCD_G[11:7], sCCD_B[11:2]}),
.WR1(sCCD_DVAL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(1280*1024),
.WR1_LENGTH(9'h100),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(CCD_PIXCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(Read),
.RD1_ADDR(0),
.RD1_MAX_ADDR(1280*1024),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(VGA_CTRL_CLK),
// SDRAM Side
.SA(oDRAM0_A[11:0]),
.BA(oDRAM0_BA),
.CS_N(oDRAM0_CS_N),
.CKE(oDRAM0_CKE),
.RAS_N(oDRAM0_RAS_N),
.CAS_N(oDRAM0_CAS_N),
.WE_N(oDRAM0_WE_N),
.DQ(DRAM_DQ[15:0]),
.DQM({oDRAM0_UDQM1,oDRAM0_LDQM0})
);
Sdram_Control_4Port sdram1 (
// HOST Side
.REF_CLK(iCLK_50),
.RESET_N(1'b1),
.CLK(sdram_ctrl_clk),
// FIFO Write Side 1
.WR1_DATA({sCCD_G[6:2], sCCD_R[11:2]}),
.WR1(sCCD_DVAL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(1280*1024),
.WR1_LENGTH(9'h100),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(CCD_PIXCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA2),
.RD1(Read),
.RD1_ADDR(0),
.RD1_MAX_ADDR(1280*1024),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(VGA_CTRL_CLK),
// SDRAM Side
.SA(oDRAM1_A[11:0]),
.BA(oDRAM1_BA),
.CS_N(oDRAM1_CS_N),
.CKE(oDRAM1_CKE),
.RAS_N(oDRAM1_RAS_N),
.CAS_N(oDRAM1_CAS_N),
.WE_N(oDRAM1_WE_N),
.DQ(DRAM_DQ[31:16]),
.DQM({oDRAM1_UDQM1,oDRAM1_LDQM0})
);
// HOST Side
.REF_CLK(iCLK_50),
.RESET_N(1'b1),
.CLK(sdram_ctrl_clk),
// FIFO Write Side 1
.WR1_DATA({sCCD_G[11:7], sCCD_B[11:2]}),
.WR1(sCCD_DVAL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(1280*1024),
.WR1_LENGTH(9'h100),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(CCD_PIXCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(Read),
.RD1_ADDR(0),
.RD1_MAX_ADDR(1280*1024),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(VGA_CTRL_CLK),
// SDRAM Side
.SA(oDRAM0_A[11:0]),
.BA(oDRAM0_BA),
.CS_N(oDRAM0_CS_N),
.CKE(oDRAM0_CKE),
.RAS_N(oDRAM0_RAS_N),
.CAS_N(oDRAM0_CAS_N),
.WE_N(oDRAM0_WE_N),
.DQ(DRAM_DQ[15:0]),
.DQM({oDRAM0_UDQM1,oDRAM0_LDQM0})
);
Sdram_Control_4Port sdram1 (
// HOST Side
.REF_CLK(iCLK_50),
.RESET_N(1'b1),
.CLK(sdram_ctrl_clk),
// FIFO Write Side 1
.WR1_DATA({sCCD_G[6:2], sCCD_R[11:2]}),
.WR1(sCCD_DVAL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(1280*1024),
.WR1_LENGTH(9'h100),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(CCD_PIXCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA2),
.RD1(Read),
.RD1_ADDR(0),
.RD1_MAX_ADDR(1280*1024),
.RD1_LENGTH(9'h100),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(VGA_CTRL_CLK),
// SDRAM Side
.SA(oDRAM1_A[11:0]),
.BA(oDRAM1_BA),
.CS_N(oDRAM1_CS_N),
.CKE(oDRAM1_CKE),
.RAS_N(oDRAM1_RAS_N),
.CAS_N(oDRAM1_CAS_N),
.WE_N(oDRAM1_WE_N),
.DQ(DRAM_DQ[31:16]),
.DQM({oDRAM1_UDQM1,oDRAM1_LDQM0})
);
使用兩個sdram controller是DE2-70的最大特色，既然有兩顆32MB SDRAM，就不用像DE2那樣2 read 2 write來share SDRAM頻寬，也因為SDRAM頻寬充裕，所以可以撐住XVGA(1280 x 1024)的108MHz，不糟蹋TRDB-D5M的500萬像素CMOS。
完整程式碼下載
DE2_70_D5M_XVGA.7z
Conclusion
前面提到這麼範例原本包含了Nios II與SOPC，在DE2時代，很多人跟我一樣想讓Nios II也能參與CMOS的控制，進而用C語言讀取SDRAM所capture的影像做處理，但都沒有成功，這個範例因為DE2-70的兩顆SDRAM，每顆SDRAM只用到1 read 1 write，所以將另外沒用到的read port連Nios II，看似可以成功，不過我還沒深入研究，有興趣的人可以看看。
