(原創) 如何解決DE2_LCM_CCD上下顛倒左右相反與無法設定曝光值的問題? (SOC) (DE2)
Abstract
DE2_LCM_CCD是友晶科技為DE2和其130萬像素CMOS與彩色LCD所寫的範例，但官方的範例會造成上下顛倒左右相反與曝光值無法設定的問題，本文提出解決方式。
Introduction
版權聲明：本文根據友晶科技光碟所附的範例程式加以修改，原範例版權歸友晶科技所有。
使用環境：Quartus II 7.2 SP3 + Nios II 7.2 SP3 + DE2(Cyclone II EP2C35F627C6) + TRDB_LCM + TRDB_DC2
在(原創) 如何在DE2將CCD影像顯示在彩色LCD上? (純硬體篇) (IC Design) (DE2)曾提到使用友晶科技所提供的範例將CCD的影像顯示在彩色LCD上，程式碼可在DE2_LCM_CCD.zip 或 DE2_LCM_CCD.7z下載，但這個範例在執行時會有上下顛倒左右相反與曝光值無法設定的問題，主要問題在於GPIO與I2C_CCD_Config的連線方式，只要做些小小的修改就可解決。
DE2_LCM_CCD.v / Verilog
修改過的top module
1 // --------------------------------------------------------------------
2 // Copyright (c) 2005 by Terasic Technologies Inc.
3 // --------------------------------------------------------------------
4 //
5 // Permission:
6 //
7 // Terasic grants permission to use and modify this code for use
8 // in synthesis for all Terasic Development Boards and Altera Development
9 // Kits made by Terasic. Other use of this code, including the selling
10 // ,duplication, or modification of any portion is strictly prohibited.
11 //
12 // Disclaimer:
13 //
14 // This VHDL/Verilog or C/C++ source code is intended as a design reference
15 // which illustrates how these types of functions can be implemented.
16 // It is the user's responsibility to verify their design for
17 // consistency and functionality through the use of formal
18 // verification methods. Terasic provides no warranty regarding the use
19 // or functionality of this code.
20 //
21 // --------------------------------------------------------------------
22 //
23 // Terasic Technologies Inc
24 // 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
25 // HsinChu County, Taiwan
26 // 302
27 //
28 // web: http://www.terasic.com/
29 // email: support@terasic.com
30 //
31 // --------------------------------------------------------------------
32 //
33 // Major Functions: DE2 LCD Module + CMOS Sensor
34 //
35 // --------------------------------------------------------------------
36 //
37 // Revision History :
38 // --------------------------------------------------------------------
39 // Ver :| Author :| Mod. Date :| Changes Made:
40 // V1.0 :| Johnny Chen :| 06/03/29 :| Initial Revision
41 // --------------------------------------------------------------------
42
43 module DE2_LCM_CCD (
44 ////////////////////// Clock Input ////////////////////
45 CLOCK_27, // 27 MHz
46 CLOCK_50, // 50 MHz
47 EXT_CLOCK, // External Clock
48 ////////////////////// Push Button ////////////////////
49 KEY, // Pushbutton[3:0]
50 //////////////////// DPDT Switch ////////////////////
51 SW, // Toggle Switch[17:0]
52 ////////////////////// 7-SEG Dispaly ////////////////////
53 HEX0, // Seven Segment Digit 0
54 HEX1, // Seven Segment Digit 1
55 HEX2, // Seven Segment Digit 2
56 HEX3, // Seven Segment Digit 3
57 HEX4, // Seven Segment Digit 4
58 HEX5, // Seven Segment Digit 5
59 HEX6, // Seven Segment Digit 6
60 HEX7, // Seven Segment Digit 7
61 ////////////////////// LED ////////////////////////
62 LEDG, // LED Green[8:0]
63 LEDR, // LED Red[17:0]
64 ////////////////////// UART ////////////////////////
65 UART_TXD, // UART Transmitter
66 UART_RXD, // UART Receiver
67 ////////////////////// IRDA ////////////////////////
68 IRDA_TXD, // IRDA Transmitter
69 IRDA_RXD, // IRDA Receiver
70 ////////////////////// SDRAM Interface ////////////////
71 DRAM_DQ, // SDRAM Data bus 16 Bits
72 DRAM_ADDR, // SDRAM Address bus 12 Bits
73 DRAM_LDQM, // SDRAM Low-byte Data Mask
74 DRAM_UDQM, // SDRAM High-byte Data Mask
75 DRAM_WE_N, // SDRAM Write Enable
76 DRAM_CAS_N, // SDRAM Column Address Strobe
77 DRAM_RAS_N, // SDRAM Row Address Strobe
78 DRAM_CS_N, // SDRAM Chip Select
79 DRAM_BA_0, // SDRAM Bank Address 0
80 DRAM_BA_1, // SDRAM Bank Address 0
81 DRAM_CLK, // SDRAM Clock
82 DRAM_CKE, // SDRAM Clock Enable
83 ////////////////////// Flash Interface ////////////////
84 FL_DQ, // FLASH Data bus 8 Bits
85 FL_ADDR, // FLASH Address bus 22 Bits
86 FL_WE_N, // FLASH Write Enable
87 FL_RST_N, // FLASH Reset
88 FL_OE_N, // FLASH Output Enable
89 FL_CE_N, // FLASH Chip Enable
90 ////////////////////// SRAM Interface ////////////////
91 SRAM_DQ, // SRAM Data bus 16 Bits
92 SRAM_ADDR, // SRAM Address bus 18 Bits
93 SRAM_UB_N, // SRAM High-byte Data Mask
94 SRAM_LB_N, // SRAM Low-byte Data Mask
95 SRAM_WE_N, // SRAM Write Enable
96 SRAM_CE_N, // SRAM Chip Enable
97 SRAM_OE_N, // SRAM Output Enable
98 ////////////////////// ISP1362 Interface ////////////////
99 OTG_DATA, // ISP1362 Data bus 16 Bits
100 OTG_ADDR, // ISP1362 Address 2 Bits
101 OTG_CS_N, // ISP1362 Chip Select
102 OTG_RD_N, // ISP1362 Write
103 OTG_WR_N, // ISP1362 Read
104 OTG_RST_N, // ISP1362 Reset
105 OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
106 OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
107 OTG_INT0, // ISP1362 Interrupt 0
108 OTG_INT1, // ISP1362 Interrupt 1
109 OTG_DREQ0, // ISP1362 DMA Request 0
110 OTG_DREQ1, // ISP1362 DMA Request 1
111 OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
112 OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
113 ////////////////////// LCD Module 16X2 ////////////////
114 LCD_ON, // LCD Power ON/OFF
115 LCD_BLON, // LCD Back Light ON/OFF
116 LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
117 LCD_EN, // LCD Enable
118 LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
119 LCD_DATA, // LCD Data bus 8 bits
120 ////////////////////// SD_Card Interface ////////////////
121 SD_DAT, // SD Card Data
122 SD_DAT3, // SD Card Data 3
123 SD_CMD, // SD Card Command Signal
124 SD_CLK, // SD Card Clock
125 ////////////////////// USB JTAG link ////////////////////
126 TDI, // CPLD -> FPGA (data in)
127 TCK, // CPLD -> FPGA (clk)
128 TCS, // CPLD -> FPGA (CS)
129 TDO, // FPGA -> CPLD (data out)
130 ////////////////////// I2C ////////////////////////////
131 I2C_SDAT, // I2C Data
132 I2C_SCLK, // I2C Clock
133 ////////////////////// PS2 ////////////////////////////
134 PS2_DAT, // PS2 Data
135 PS2_CLK, // PS2 Clock
136 ////////////////////// VGA ////////////////////////////
137 VGA_CLK, // VGA Clock
138 VGA_HS, // VGA H_SYNC
139 VGA_VS, // VGA V_SYNC
140 VGA_BLANK, // VGA BLANK
141 VGA_SYNC, // VGA SYNC
142 VGA_R, // VGA Red[9:0]
143 VGA_G, // VGA Green[9:0]
144 VGA_B, // VGA Blue[9:0]
145 ////////////////////// Ethernet Interface ////////////////////////
146 ENET_DATA, // DM9000A DATA bus 16Bits
147 ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
148 ENET_CS_N, // DM9000A Chip Select
149 ENET_WR_N, // DM9000A Write
150 ENET_RD_N, // DM9000A Read
151 ENET_RST_N, // DM9000A Reset
152 ENET_INT, // DM9000A Interrupt
153 ENET_CLK, // DM9000A Clock 25 MHz
154 ////////////////////// Audio CODEC ////////////////////////
155 AUD_ADCLRCK, // Audio CODEC ADC LR Clock
156 AUD_ADCDAT, // Audio CODEC ADC Data
157 AUD_DACLRCK, // Audio CODEC DAC LR Clock
158 AUD_DACDAT, // Audio CODEC DAC Data
159 AUD_BCLK, // Audio CODEC Bit-Stream Clock
160 AUD_XCK, // Audio CODEC Chip Clock
161 ////////////////////// TV Decoder ////////////////////////
162 TD_DATA, // TV Decoder Data bus 8 bits
163 TD_HS, // TV Decoder H_SYNC
164 TD_VS, // TV Decoder V_SYNC
165 TD_RESET, // TV Decoder Reset
166 ////////////////////// GPIO ////////////////////////////
167 GPIO_0, // GPIO Connection 0
168 GPIO_1 // GPIO Connection 1
169 );
170
171 ////////////////////////////// Clock Input ////////////////////////
172 input CLOCK_27; // 27 MHz
173 input CLOCK_50; // 50 MHz
174 input EXT_CLOCK; // External Clock
175 ////////////////////////////// Push Button ////////////////////////
176 input [3:0] KEY; // Pushbutton[3:0]
177 ////////////////////////////// DPDT Switch ////////////////////////
178 input [17:0] SW; // Toggle Switch[17:0]
179 ////////////////////////////// 7-SEG Dispaly ////////////////////////
180 output [6:0] HEX0; // Seven Segment Digit 0
181 output [6:0] HEX1; // Seven Segment Digit 1
182 output [6:0] HEX2; // Seven Segment Digit 2
183 output [6:0] HEX3; // Seven Segment Digit 3
184 output [6:0] HEX4; // Seven Segment Digit 4
185 output [6:0] HEX5; // Seven Segment Digit 5
186 output [6:0] HEX6; // Seven Segment Digit 6
187 output [6:0] HEX7; // Seven Segment Digit 7
188 ////////////////////////////// LED ////////////////////////////
189 output [8:0] LEDG; // LED Green[8:0]
190 output [17:0] LEDR; // LED Red[17:0]
191 ////////////////////////////// UART ////////////////////////////
192 output UART_TXD; // UART Transmitter
193 input UART_RXD; // UART Receiver
194 ////////////////////////////// IRDA ////////////////////////////
195 output IRDA_TXD; // IRDA Transmitter
196 input IRDA_RXD; // IRDA Receiver
197 ////////////////////////////// SDRAM Interface ////////////////////////
198 inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
199 output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
200 output DRAM_LDQM; // SDRAM Low-byte Data Mask
201 output DRAM_UDQM; // SDRAM High-byte Data Mask
202 output DRAM_WE_N; // SDRAM Write Enable
203 output DRAM_CAS_N; // SDRAM Column Address Strobe
204 output DRAM_RAS_N; // SDRAM Row Address Strobe
205 output DRAM_CS_N; // SDRAM Chip Select
206 output DRAM_BA_0; // SDRAM Bank Address 0
207 output DRAM_BA_1; // SDRAM Bank Address 0
208 output DRAM_CLK; // SDRAM Clock
209 output DRAM_CKE; // SDRAM Clock Enable
210 ////////////////////////////// Flash Interface ////////////////////////
211 inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
212 output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
213 output FL_WE_N; // FLASH Write Enable
214 output FL_RST_N; // FLASH Reset
215 output FL_OE_N; // FLASH Output Enable
216 output FL_CE_N; // FLASH Chip Enable
217 ////////////////////////////// SRAM Interface ////////////////////////
218 inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
219 output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
220 output SRAM_UB_N; // SRAM High-byte Data Mask
221 output SRAM_LB_N; // SRAM Low-byte Data Mask
222 output SRAM_WE_N; // SRAM Write Enable
223 output SRAM_CE_N; // SRAM Chip Enable
224 output SRAM_OE_N; // SRAM Output Enable
225 ////////////////////////////// ISP1362 Interface ////////////////////////
226 inout [15:0] OTG_DATA; // ISP1362 Data bus 16 Bits
227 output [1:0] OTG_ADDR; // ISP1362 Address 2 Bits
228 output OTG_CS_N; // ISP1362 Chip Select
229 output OTG_RD_N; // ISP1362 Write
230 output OTG_WR_N; // ISP1362 Read
231 output OTG_RST_N; // ISP1362 Reset
232 output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
233 output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
234 input OTG_INT0; // ISP1362 Interrupt 0
235 input OTG_INT1; // ISP1362 Interrupt 1
236 input OTG_DREQ0; // ISP1362 DMA Request 0
237 input OTG_DREQ1; // ISP1362 DMA Request 1
238 output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
239 output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
240 ////////////////////////////// LCD Module 16X2 ////////////////////////////
241 inout [7:0] LCD_DATA; // LCD Data bus 8 bits
242 output LCD_ON; // LCD Power ON/OFF
243 output LCD_BLON; // LCD Back Light ON/OFF
244 output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
245 output LCD_EN; // LCD Enable
246 output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
247 ////////////////////////////// SD Card Interface ////////////////////////
248 inout SD_DAT; // SD Card Data
249 inout SD_DAT3; // SD Card Data 3
250 inout SD_CMD; // SD Card Command Signal
251 output SD_CLK; // SD Card Clock
252 ////////////////////////////// I2C ////////////////////////////////
253 inout I2C_SDAT; // I2C Data
254 output I2C_SCLK; // I2C Clock
255 ////////////////////////////// PS2 ////////////////////////////////
256 input PS2_DAT; // PS2 Data
257 input PS2_CLK; // PS2 Clock
258 ////////////////////////////// USB JTAG link ////////////////////////////
259 input TDI; // CPLD -> FPGA (data in)
260 input TCK; // CPLD -> FPGA (clk)
261 input TCS; // CPLD -> FPGA (CS)
262 output TDO; // FPGA -> CPLD (data out)
263 ////////////////////////////// VGA ////////////////////////////
264 output VGA_CLK; // VGA Clock
265 output VGA_HS; // VGA H_SYNC
266 output VGA_VS; // VGA V_SYNC
267 output VGA_BLANK; // VGA BLANK
268 output VGA_SYNC; // VGA SYNC
269 output [9:0] VGA_R; // VGA Red[9:0]
270 output [9:0] VGA_G; // VGA Green[9:0]
271 output [9:0] VGA_B; // VGA Blue[9:0]
272 ////////////////////////////// Ethernet Interface ////////////////////////////
273 inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
274 output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
275 output ENET_CS_N; // DM9000A Chip Select
276 output ENET_WR_N; // DM9000A Write
277 output ENET_RD_N; // DM9000A Read
278 output ENET_RST_N; // DM9000A Reset
279 input ENET_INT; // DM9000A Interrupt
280 output ENET_CLK; // DM9000A Clock 25 MHz
281 ////////////////////////////// Audio CODEC ////////////////////////////
282 inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
283 input AUD_ADCDAT; // Audio CODEC ADC Data
284 inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
285 output AUD_DACDAT; // Audio CODEC DAC Data
286 inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
287 output AUD_XCK; // Audio CODEC Chip Clock
288 ////////////////////////////// TV Devoder ////////////////////////////
289 input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
290 input TD_HS; // TV Decoder H_SYNC
291 input TD_VS; // TV Decoder V_SYNC
292 output TD_RESET; // TV Decoder Reset
293 ////////////////////////////// GPIO ////////////////////////////////
294 inout [35:0] GPIO_0; // GPIO Connection 0
295 inout [35:0] GPIO_1; // GPIO Connection 1
296
297 // Turn on all display
298 assign LCD_ON = 1'b1;
299 assign LCD_BLON = 1'b1;
300
301 // All inout port turn to tri-state
302 assign DRAM_DQ = 16'hzzzz;
303 assign FL_DQ = 8'hzz;
304 assign SRAM_DQ = 16'hzzzz;
305 assign OTG_DATA = 16'hzzzz;
306 assign LCD_DATA = 8'hzz;
307 assign SD_DAT = 1'bz;
308 assign ENET_DATA = 16'hzzzz;
309 assign AUD_ADCLRCK = 1'bz;
310 assign AUD_DACLRCK = 1'bz;
311 assign AUD_BCLK = 1'bz;
312 assign TD_RESET = 1'b1;
313
314 //////////////////////// For TFT LCD Module ///////////////////////
315 wire [7:0] LCM_DATA; // LCM Data 8 Bits
316 wire LCM_GRST; // LCM Global Reset
317 wire LCM_SHDB; // LCM Sleep Mode
318 wire LCM_DCLK; // LCM Clcok
319 wire LCM_HSYNC; // LCM HSYNC
320 wire LCM_VSYNC; // LCM VSYNC
321 wire LCM_SCLK; // LCM I2C Clock
322 wire LCM_SDAT; // LCM I2C Data
323 wire LCM_SCEN; // LCM I2C Enable
324 wire CLK_18;
325
326 assign GPIO_0[18] = LCM_DATA[6];
327 assign GPIO_0[19] = LCM_DATA[7];
328 assign GPIO_0[20] = LCM_DATA[4];
329 assign GPIO_0[21] = LCM_DATA[5];
330 assign GPIO_0[22] = LCM_DATA[2];
331 assign GPIO_0[23] = LCM_DATA[3];
332 assign GPIO_0[24] = LCM_DATA[0];
333 assign GPIO_0[25] = LCM_DATA[1];
334 assign GPIO_0[26] = LCM_VSYNC;
335 assign GPIO_0[28] = LCM_SCLK;
336 assign GPIO_0[29] = LCM_DCLK;
337 assign GPIO_0[30] = LCM_GRST;
338 assign GPIO_0[31] = LCM_SHDB;
339 assign GPIO_0[33] = LCM_SCEN;
340 assign GPIO_0[34] = LCM_SDAT;
341 assign GPIO_0[35] = LCM_HSYNC;
342
343 //////////////////////// For CMOS Sensor 1 ///////////////////////
344 wire [9:0] CCD_DATA;
345 wire CCD_SDAT;
346 wire CCD_SCLK;
347 wire CCD_FLASH;
348 wire CCD_FVAL;
349 wire CCD_LVAL;
350 wire CCD_PIXCLK;
351 reg CCD_MCLK; // CCD Master Clock
352
353 wire [15:0] Read_DATA1;
354 wire [15:0] Read_DATA2;
355 wire [9:0] mCCD_DATA;
356 wire mCCD_DVAL;
357 wire mCCD_DVAL_d;
358 wire [10:0] X_Cont;
359 wire [10:0] Y_Cont;
360 wire [9:0] X_ADDR;
361 wire [31:0] Frame_Cont;
362 wire [9:0] mCCD_R;
363 wire [9:0] mCCD_G;
364 wire [9:0] mCCD_B;
365 wire DLY_RST_0;
366 wire DLY_RST_1;
367 wire DLY_RST_2;
368 wire Read;
369 reg [9:0] rCCD_DATA;
370 reg rCCD_LVAL;
371 reg rCCD_FVAL;
372 wire [9:0] sCCD_R;
373 wire [9:0] sCCD_G;
374 wire [9:0] sCCD_B;
375 wire sCCD_DVAL;
376
377
378 assign CCD_DATA[0] = GPIO_1[0];
379 assign CCD_DATA[1] = GPIO_1[1];
380 assign CCD_DATA[2] = GPIO_1[5];
381 assign CCD_DATA[3] = GPIO_1[3];
382 assign CCD_DATA[4] = GPIO_1[2];
383 assign CCD_DATA[5] = GPIO_1[4];
384 assign CCD_DATA[6] = GPIO_1[6];
385 assign CCD_DATA[7] = GPIO_1[7];
386 assign CCD_DATA[8] = GPIO_1[8];
387 assign CCD_DATA[9] = GPIO_1[9];
388 assign GPIO_1[11] = CCD_MCLK;
389 assign CCD_FVAL = GPIO_1[13];
390 assign CCD_LVAL = GPIO_1[12];
391 assign CCD_PIXCLK = GPIO_1[10];
392
393 always@(posedge CLOCK_50)
394 CCD_MCLK <= ~CCD_MCLK;
395
396 always@(posedge CCD_PIXCLK) begin
397 rCCD_DATA <= CCD_DATA;
398 rCCD_LVAL <= CCD_LVAL;
399 rCCD_FVAL <= CCD_FVAL;
400 end
401
402 LCM_PLL u0 (
403 .inclk0(CLOCK_27),
404 .c0(CLK_18)
405 );
406
407 LCM_Controller u1 (
408 // Host Side
409 .iRed(Read_DATA2[9:2]),
410 .iGreen({Read_DATA1[14:10],Read_DATA2[14:12]}),
411 .iBlue(Read_DATA1[9:2]),
412 // LCM Side
413 .LCM_DATA(LCM_DATA),
414 .LCM_VSYNC(LCM_VSYNC),
415 .LCM_HSYNC(LCM_HSYNC),
416 .LCM_DCLK(LCM_DCLK),
417 .LCM_SHDB(LCM_SHDB),
418 .LCM_GRST(LCM_GRST),
419 // Control Signals
420 .oDATA_REQ(Read),
421 .iCLK(CLK_18),
422 .iRST_N(DLY_RST_2)
423 );
424
425 Reset_Delay u2 (
426 .iCLK(CLOCK_50),
427 .iRST(KEY[0]),
428 .oRST_0(DLY_RST_0),
429 .oRST_1(DLY_RST_1),
430 .oRST_2(DLY_RST_2)
431 );
432
433 CCD_Capture u3 (
434 .oDATA(mCCD_DATA),
435 .oDVAL(mCCD_DVAL),
436 .oX_Cont(X_Cont),
437 .oY_Cont(Y_Cont),
438 .oFrame_Cont(Frame_Cont),
439 .iDATA(rCCD_DATA),
440 .iFVAL(rCCD_FVAL),
441 .iLVAL(rCCD_LVAL),
442 .iSTART(!KEY[3]),
443 .iEND(!KEY[2]),
444 .iCLK(CCD_PIXCLK),
445 .iRST(DLY_RST_1)
446 );
447
448 RAW2RGB u4 (
449 .oRed(mCCD_R),
450 .oGreen(mCCD_G),
451 .oBlue(mCCD_B),
452 .oDVAL(mCCD_DVAL_d),
453 .iX_Cont(X_Cont),
454 .iY_Cont(Y_Cont),
455 .iDATA(mCCD_DATA),
456 .iDVAL(mCCD_DVAL),
457 .iCLK(CCD_PIXCLK),
458 .iRST(DLY_RST_1)
459 );
460
461 SEG7_LUT_8 u5 (
462 .oSEG0(HEX0),
463 .oSEG1(HEX1),
464 .oSEG2(HEX2),
465 .oSEG3(HEX3),
466 .oSEG4(HEX4),
467 .oSEG5(HEX5),
468 .oSEG6(HEX6),
469 .oSEG7(HEX7),
470 .iDIG(Frame_Cont)
471 );
472
473 Sdram_Control_4Port u6 (
474 // HOST Side
475 .REF_CLK(CLOCK_50),
476 .RESET_N(1'b1),
477 // FIFO Write Side 1
478 .WR1_DATA({sCCD_G[9:5], sCCD_B[9:0]}),
479 .WR1(sCCD_DVAL),
480 .WR1_ADDR(0),
481 .WR1_MAX_ADDR(320*256),
482 .WR1_LENGTH(9'h100),
483 .WR1_LOAD(!DLY_RST_0),
484 .WR1_CLK(CCD_PIXCLK),
485 // FIFO Write Side 2
486 .WR2_DATA( {sCCD_G[4:0], sCCD_R[9:0]}),
487 .WR2(sCCD_DVAL),
488 .WR2_ADDR(22'h100000),
489 .WR2_MAX_ADDR(22'h100000+320*256),
490 .WR2_LENGTH(9'h100),
491 .WR2_LOAD(!DLY_RST_0),
492 .WR2_CLK(CCD_PIXCLK),
493 // FIFO Read Side 1
494 .RD1_DATA(Read_DATA1),
495 .RD1(Read),
496 .RD1_ADDR(320*8),
497 .RD1_MAX_ADDR(320*248),
498 .RD1_LENGTH(9'h100),
499 .RD1_LOAD(!DLY_RST_0),
500 .RD1_CLK(CLK_18),
501 // FIFO Read Side 2
502 .RD2_DATA(Read_DATA2),
503 .RD2(Read),
504 .RD2_ADDR(22'h100000+320*8),
505 .RD2_MAX_ADDR(22'h100000+320*248),
506 .RD2_LENGTH(9'h100),
507 .RD2_LOAD(!DLY_RST_0),
508 .RD2_CLK(CLK_18),
509 // SDRAM Side
510 .SA(DRAM_ADDR),
511 .BA({DRAM_BA_1,DRAM_BA_0}),
512 .CS_N(DRAM_CS_N),
513 .CKE(DRAM_CKE),
514 .RAS_N(DRAM_RAS_N),
515 .CAS_N(DRAM_CAS_N),
516 .WE_N(DRAM_WE_N),
517 .DQ(DRAM_DQ),
518 .DQM({DRAM_UDQM,DRAM_LDQM}),
519 .SDR_CLK(DRAM_CLK)
520 );
521
522 I2C_CCD_Config u7 (
523 // Host Side
524 .iCLK(CLOCK_50),
525 .iRST_N(KEY[1]),
526 .iExposure(SW[15:0]),
527 // I2C Side
528 .I2C_SCLK(GPIO_1[14]),
529 .I2C_SDAT(GPIO_1[15])
530 );
531
532 I2S_LCM_Config u8 (
533 // Host Side
534 .iCLK(CLOCK_50),
535 .iRST_N(KEY[0]),
536 // I2C Side
537 .I2S_SCLK(LCM_SCLK),
538 .I2S_SDAT(LCM_SDAT),
539 .I2S_SCEN(LCM_SCEN)
540 );
541
542 I2C_AV_Config u9 (
543 // Host Side
544 .iCLK(CLOCK_50),
545 .iRST_N(KEY[0]),
546 // I2C Side
547 .I2C_SCLK(I2C_SCLK),
548 .I2C_SDAT(I2C_SDAT)
549 );
550
551 Mirror_Col u10 (
552 // Input Side
553 .iCCD_R(mCCD_R),
554 .iCCD_G(mCCD_G),
555 .iCCD_B(mCCD_B),
556 .iCCD_DVAL(mCCD_DVAL_d),
557 .iCCD_PIXCLK(CCD_PIXCLK),
558 .iRST_N(DLY_RST_1),
559 // Output Side
560 .oCCD_R(sCCD_R),
561 .oCCD_G(sCCD_G),
562 .oCCD_B(sCCD_B),
563 .oCCD_DVAL(sCCD_DVAL)
564 );
565
566 endmodule
2 // Copyright (c) 2005 by Terasic Technologies Inc.
3 // --------------------------------------------------------------------
4 //
5 // Permission:
6 //
7 // Terasic grants permission to use and modify this code for use
8 // in synthesis for all Terasic Development Boards and Altera Development
9 // Kits made by Terasic. Other use of this code, including the selling
10 // ,duplication, or modification of any portion is strictly prohibited.
11 //
12 // Disclaimer:
13 //
14 // This VHDL/Verilog or C/C++ source code is intended as a design reference
15 // which illustrates how these types of functions can be implemented.
16 // It is the user's responsibility to verify their design for
17 // consistency and functionality through the use of formal
18 // verification methods. Terasic provides no warranty regarding the use
19 // or functionality of this code.
20 //
21 // --------------------------------------------------------------------
22 //
23 // Terasic Technologies Inc
24 // 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
25 // HsinChu County, Taiwan
26 // 302
27 //
28 // web: http://www.terasic.com/
29 // email: support@terasic.com
30 //
31 // --------------------------------------------------------------------
32 //
33 // Major Functions: DE2 LCD Module + CMOS Sensor
34 //
35 // --------------------------------------------------------------------
36 //
37 // Revision History :
38 // --------------------------------------------------------------------
39 // Ver :| Author :| Mod. Date :| Changes Made:
40 // V1.0 :| Johnny Chen :| 06/03/29 :| Initial Revision
41 // --------------------------------------------------------------------
42
43 module DE2_LCM_CCD (
44 ////////////////////// Clock Input ////////////////////
45 CLOCK_27, // 27 MHz
46 CLOCK_50, // 50 MHz
47 EXT_CLOCK, // External Clock
48 ////////////////////// Push Button ////////////////////
49 KEY, // Pushbutton[3:0]
50 //////////////////// DPDT Switch ////////////////////
51 SW, // Toggle Switch[17:0]
52 ////////////////////// 7-SEG Dispaly ////////////////////
53 HEX0, // Seven Segment Digit 0
54 HEX1, // Seven Segment Digit 1
55 HEX2, // Seven Segment Digit 2
56 HEX3, // Seven Segment Digit 3
57 HEX4, // Seven Segment Digit 4
58 HEX5, // Seven Segment Digit 5
59 HEX6, // Seven Segment Digit 6
60 HEX7, // Seven Segment Digit 7
61 ////////////////////// LED ////////////////////////
62 LEDG, // LED Green[8:0]
63 LEDR, // LED Red[17:0]
64 ////////////////////// UART ////////////////////////
65 UART_TXD, // UART Transmitter
66 UART_RXD, // UART Receiver
67 ////////////////////// IRDA ////////////////////////
68 IRDA_TXD, // IRDA Transmitter
69 IRDA_RXD, // IRDA Receiver
70 ////////////////////// SDRAM Interface ////////////////
71 DRAM_DQ, // SDRAM Data bus 16 Bits
72 DRAM_ADDR, // SDRAM Address bus 12 Bits
73 DRAM_LDQM, // SDRAM Low-byte Data Mask
74 DRAM_UDQM, // SDRAM High-byte Data Mask
75 DRAM_WE_N, // SDRAM Write Enable
76 DRAM_CAS_N, // SDRAM Column Address Strobe
77 DRAM_RAS_N, // SDRAM Row Address Strobe
78 DRAM_CS_N, // SDRAM Chip Select
79 DRAM_BA_0, // SDRAM Bank Address 0
80 DRAM_BA_1, // SDRAM Bank Address 0
81 DRAM_CLK, // SDRAM Clock
82 DRAM_CKE, // SDRAM Clock Enable
83 ////////////////////// Flash Interface ////////////////
84 FL_DQ, // FLASH Data bus 8 Bits
85 FL_ADDR, // FLASH Address bus 22 Bits
86 FL_WE_N, // FLASH Write Enable
87 FL_RST_N, // FLASH Reset
88 FL_OE_N, // FLASH Output Enable
89 FL_CE_N, // FLASH Chip Enable
90 ////////////////////// SRAM Interface ////////////////
91 SRAM_DQ, // SRAM Data bus 16 Bits
92 SRAM_ADDR, // SRAM Address bus 18 Bits
93 SRAM_UB_N, // SRAM High-byte Data Mask
94 SRAM_LB_N, // SRAM Low-byte Data Mask
95 SRAM_WE_N, // SRAM Write Enable
96 SRAM_CE_N, // SRAM Chip Enable
97 SRAM_OE_N, // SRAM Output Enable
98 ////////////////////// ISP1362 Interface ////////////////
99 OTG_DATA, // ISP1362 Data bus 16 Bits
100 OTG_ADDR, // ISP1362 Address 2 Bits
101 OTG_CS_N, // ISP1362 Chip Select
102 OTG_RD_N, // ISP1362 Write
103 OTG_WR_N, // ISP1362 Read
104 OTG_RST_N, // ISP1362 Reset
105 OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
106 OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
107 OTG_INT0, // ISP1362 Interrupt 0
108 OTG_INT1, // ISP1362 Interrupt 1
109 OTG_DREQ0, // ISP1362 DMA Request 0
110 OTG_DREQ1, // ISP1362 DMA Request 1
111 OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
112 OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
113 ////////////////////// LCD Module 16X2 ////////////////
114 LCD_ON, // LCD Power ON/OFF
115 LCD_BLON, // LCD Back Light ON/OFF
116 LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
117 LCD_EN, // LCD Enable
118 LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
119 LCD_DATA, // LCD Data bus 8 bits
120 ////////////////////// SD_Card Interface ////////////////
121 SD_DAT, // SD Card Data
122 SD_DAT3, // SD Card Data 3
123 SD_CMD, // SD Card Command Signal
124 SD_CLK, // SD Card Clock
125 ////////////////////// USB JTAG link ////////////////////
126 TDI, // CPLD -> FPGA (data in)
127 TCK, // CPLD -> FPGA (clk)
128 TCS, // CPLD -> FPGA (CS)
129 TDO, // FPGA -> CPLD (data out)
130 ////////////////////// I2C ////////////////////////////
131 I2C_SDAT, // I2C Data
132 I2C_SCLK, // I2C Clock
133 ////////////////////// PS2 ////////////////////////////
134 PS2_DAT, // PS2 Data
135 PS2_CLK, // PS2 Clock
136 ////////////////////// VGA ////////////////////////////
137 VGA_CLK, // VGA Clock
138 VGA_HS, // VGA H_SYNC
139 VGA_VS, // VGA V_SYNC
140 VGA_BLANK, // VGA BLANK
141 VGA_SYNC, // VGA SYNC
142 VGA_R, // VGA Red[9:0]
143 VGA_G, // VGA Green[9:0]
144 VGA_B, // VGA Blue[9:0]
145 ////////////////////// Ethernet Interface ////////////////////////
146 ENET_DATA, // DM9000A DATA bus 16Bits
147 ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
148 ENET_CS_N, // DM9000A Chip Select
149 ENET_WR_N, // DM9000A Write
150 ENET_RD_N, // DM9000A Read
151 ENET_RST_N, // DM9000A Reset
152 ENET_INT, // DM9000A Interrupt
153 ENET_CLK, // DM9000A Clock 25 MHz
154 ////////////////////// Audio CODEC ////////////////////////
155 AUD_ADCLRCK, // Audio CODEC ADC LR Clock
156 AUD_ADCDAT, // Audio CODEC ADC Data
157 AUD_DACLRCK, // Audio CODEC DAC LR Clock
158 AUD_DACDAT, // Audio CODEC DAC Data
159 AUD_BCLK, // Audio CODEC Bit-Stream Clock
160 AUD_XCK, // Audio CODEC Chip Clock
161 ////////////////////// TV Decoder ////////////////////////
162 TD_DATA, // TV Decoder Data bus 8 bits
163 TD_HS, // TV Decoder H_SYNC
164 TD_VS, // TV Decoder V_SYNC
165 TD_RESET, // TV Decoder Reset
166 ////////////////////// GPIO ////////////////////////////
167 GPIO_0, // GPIO Connection 0
168 GPIO_1 // GPIO Connection 1
169 );
170
171 ////////////////////////////// Clock Input ////////////////////////
172 input CLOCK_27; // 27 MHz
173 input CLOCK_50; // 50 MHz
174 input EXT_CLOCK; // External Clock
175 ////////////////////////////// Push Button ////////////////////////
176 input [3:0] KEY; // Pushbutton[3:0]
177 ////////////////////////////// DPDT Switch ////////////////////////
178 input [17:0] SW; // Toggle Switch[17:0]
179 ////////////////////////////// 7-SEG Dispaly ////////////////////////
180 output [6:0] HEX0; // Seven Segment Digit 0
181 output [6:0] HEX1; // Seven Segment Digit 1
182 output [6:0] HEX2; // Seven Segment Digit 2
183 output [6:0] HEX3; // Seven Segment Digit 3
184 output [6:0] HEX4; // Seven Segment Digit 4
185 output [6:0] HEX5; // Seven Segment Digit 5
186 output [6:0] HEX6; // Seven Segment Digit 6
187 output [6:0] HEX7; // Seven Segment Digit 7
188 ////////////////////////////// LED ////////////////////////////
189 output [8:0] LEDG; // LED Green[8:0]
190 output [17:0] LEDR; // LED Red[17:0]
191 ////////////////////////////// UART ////////////////////////////
192 output UART_TXD; // UART Transmitter
193 input UART_RXD; // UART Receiver
194 ////////////////////////////// IRDA ////////////////////////////
195 output IRDA_TXD; // IRDA Transmitter
196 input IRDA_RXD; // IRDA Receiver
197 ////////////////////////////// SDRAM Interface ////////////////////////
198 inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
199 output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
200 output DRAM_LDQM; // SDRAM Low-byte Data Mask
201 output DRAM_UDQM; // SDRAM High-byte Data Mask
202 output DRAM_WE_N; // SDRAM Write Enable
203 output DRAM_CAS_N; // SDRAM Column Address Strobe
204 output DRAM_RAS_N; // SDRAM Row Address Strobe
205 output DRAM_CS_N; // SDRAM Chip Select
206 output DRAM_BA_0; // SDRAM Bank Address 0
207 output DRAM_BA_1; // SDRAM Bank Address 0
208 output DRAM_CLK; // SDRAM Clock
209 output DRAM_CKE; // SDRAM Clock Enable
210 ////////////////////////////// Flash Interface ////////////////////////
211 inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
212 output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
213 output FL_WE_N; // FLASH Write Enable
214 output FL_RST_N; // FLASH Reset
215 output FL_OE_N; // FLASH Output Enable
216 output FL_CE_N; // FLASH Chip Enable
217 ////////////////////////////// SRAM Interface ////////////////////////
218 inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
219 output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
220 output SRAM_UB_N; // SRAM High-byte Data Mask
221 output SRAM_LB_N; // SRAM Low-byte Data Mask
222 output SRAM_WE_N; // SRAM Write Enable
223 output SRAM_CE_N; // SRAM Chip Enable
224 output SRAM_OE_N; // SRAM Output Enable
225 ////////////////////////////// ISP1362 Interface ////////////////////////
226 inout [15:0] OTG_DATA; // ISP1362 Data bus 16 Bits
227 output [1:0] OTG_ADDR; // ISP1362 Address 2 Bits
228 output OTG_CS_N; // ISP1362 Chip Select
229 output OTG_RD_N; // ISP1362 Write
230 output OTG_WR_N; // ISP1362 Read
231 output OTG_RST_N; // ISP1362 Reset
232 output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
233 output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
234 input OTG_INT0; // ISP1362 Interrupt 0
235 input OTG_INT1; // ISP1362 Interrupt 1
236 input OTG_DREQ0; // ISP1362 DMA Request 0
237 input OTG_DREQ1; // ISP1362 DMA Request 1
238 output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
239 output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
240 ////////////////////////////// LCD Module 16X2 ////////////////////////////
241 inout [7:0] LCD_DATA; // LCD Data bus 8 bits
242 output LCD_ON; // LCD Power ON/OFF
243 output LCD_BLON; // LCD Back Light ON/OFF
244 output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
245 output LCD_EN; // LCD Enable
246 output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
247 ////////////////////////////// SD Card Interface ////////////////////////
248 inout SD_DAT; // SD Card Data
249 inout SD_DAT3; // SD Card Data 3
250 inout SD_CMD; // SD Card Command Signal
251 output SD_CLK; // SD Card Clock
252 ////////////////////////////// I2C ////////////////////////////////
253 inout I2C_SDAT; // I2C Data
254 output I2C_SCLK; // I2C Clock
255 ////////////////////////////// PS2 ////////////////////////////////
256 input PS2_DAT; // PS2 Data
257 input PS2_CLK; // PS2 Clock
258 ////////////////////////////// USB JTAG link ////////////////////////////
259 input TDI; // CPLD -> FPGA (data in)
260 input TCK; // CPLD -> FPGA (clk)
261 input TCS; // CPLD -> FPGA (CS)
262 output TDO; // FPGA -> CPLD (data out)
263 ////////////////////////////// VGA ////////////////////////////
264 output VGA_CLK; // VGA Clock
265 output VGA_HS; // VGA H_SYNC
266 output VGA_VS; // VGA V_SYNC
267 output VGA_BLANK; // VGA BLANK
268 output VGA_SYNC; // VGA SYNC
269 output [9:0] VGA_R; // VGA Red[9:0]
270 output [9:0] VGA_G; // VGA Green[9:0]
271 output [9:0] VGA_B; // VGA Blue[9:0]
272 ////////////////////////////// Ethernet Interface ////////////////////////////
273 inout [15:0] ENET_DATA; // DM9000A DATA bus 16Bits
274 output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
275 output ENET_CS_N; // DM9000A Chip Select
276 output ENET_WR_N; // DM9000A Write
277 output ENET_RD_N; // DM9000A Read
278 output ENET_RST_N; // DM9000A Reset
279 input ENET_INT; // DM9000A Interrupt
280 output ENET_CLK; // DM9000A Clock 25 MHz
281 ////////////////////////////// Audio CODEC ////////////////////////////
282 inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
283 input AUD_ADCDAT; // Audio CODEC ADC Data
284 inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
285 output AUD_DACDAT; // Audio CODEC DAC Data
286 inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
287 output AUD_XCK; // Audio CODEC Chip Clock
288 ////////////////////////////// TV Devoder ////////////////////////////
289 input [7:0] TD_DATA; // TV Decoder Data bus 8 bits
290 input TD_HS; // TV Decoder H_SYNC
291 input TD_VS; // TV Decoder V_SYNC
292 output TD_RESET; // TV Decoder Reset
293 ////////////////////////////// GPIO ////////////////////////////////
294 inout [35:0] GPIO_0; // GPIO Connection 0
295 inout [35:0] GPIO_1; // GPIO Connection 1
296
297 // Turn on all display
298 assign LCD_ON = 1'b1;
299 assign LCD_BLON = 1'b1;
300
301 // All inout port turn to tri-state
302 assign DRAM_DQ = 16'hzzzz;
303 assign FL_DQ = 8'hzz;
304 assign SRAM_DQ = 16'hzzzz;
305 assign OTG_DATA = 16'hzzzz;
306 assign LCD_DATA = 8'hzz;
307 assign SD_DAT = 1'bz;
308 assign ENET_DATA = 16'hzzzz;
309 assign AUD_ADCLRCK = 1'bz;
310 assign AUD_DACLRCK = 1'bz;
311 assign AUD_BCLK = 1'bz;
312 assign TD_RESET = 1'b1;
313
314 //////////////////////// For TFT LCD Module ///////////////////////
315 wire [7:0] LCM_DATA; // LCM Data 8 Bits
316 wire LCM_GRST; // LCM Global Reset
317 wire LCM_SHDB; // LCM Sleep Mode
318 wire LCM_DCLK; // LCM Clcok
319 wire LCM_HSYNC; // LCM HSYNC
320 wire LCM_VSYNC; // LCM VSYNC
321 wire LCM_SCLK; // LCM I2C Clock
322 wire LCM_SDAT; // LCM I2C Data
323 wire LCM_SCEN; // LCM I2C Enable
324 wire CLK_18;
325
326 assign GPIO_0[18] = LCM_DATA[6];
327 assign GPIO_0[19] = LCM_DATA[7];
328 assign GPIO_0[20] = LCM_DATA[4];
329 assign GPIO_0[21] = LCM_DATA[5];
330 assign GPIO_0[22] = LCM_DATA[2];
331 assign GPIO_0[23] = LCM_DATA[3];
332 assign GPIO_0[24] = LCM_DATA[0];
333 assign GPIO_0[25] = LCM_DATA[1];
334 assign GPIO_0[26] = LCM_VSYNC;
335 assign GPIO_0[28] = LCM_SCLK;
336 assign GPIO_0[29] = LCM_DCLK;
337 assign GPIO_0[30] = LCM_GRST;
338 assign GPIO_0[31] = LCM_SHDB;
339 assign GPIO_0[33] = LCM_SCEN;
340 assign GPIO_0[34] = LCM_SDAT;
341 assign GPIO_0[35] = LCM_HSYNC;
342
343 //////////////////////// For CMOS Sensor 1 ///////////////////////
344 wire [9:0] CCD_DATA;
345 wire CCD_SDAT;
346 wire CCD_SCLK;
347 wire CCD_FLASH;
348 wire CCD_FVAL;
349 wire CCD_LVAL;
350 wire CCD_PIXCLK;
351 reg CCD_MCLK; // CCD Master Clock
352
353 wire [15:0] Read_DATA1;
354 wire [15:0] Read_DATA2;
355 wire [9:0] mCCD_DATA;
356 wire mCCD_DVAL;
357 wire mCCD_DVAL_d;
358 wire [10:0] X_Cont;
359 wire [10:0] Y_Cont;
360 wire [9:0] X_ADDR;
361 wire [31:0] Frame_Cont;
362 wire [9:0] mCCD_R;
363 wire [9:0] mCCD_G;
364 wire [9:0] mCCD_B;
365 wire DLY_RST_0;
366 wire DLY_RST_1;
367 wire DLY_RST_2;
368 wire Read;
369 reg [9:0] rCCD_DATA;
370 reg rCCD_LVAL;
371 reg rCCD_FVAL;
372 wire [9:0] sCCD_R;
373 wire [9:0] sCCD_G;
374 wire [9:0] sCCD_B;
375 wire sCCD_DVAL;
376
377
378 assign CCD_DATA[0] = GPIO_1[0];
379 assign CCD_DATA[1] = GPIO_1[1];
380 assign CCD_DATA[2] = GPIO_1[5];
381 assign CCD_DATA[3] = GPIO_1[3];
382 assign CCD_DATA[4] = GPIO_1[2];
383 assign CCD_DATA[5] = GPIO_1[4];
384 assign CCD_DATA[6] = GPIO_1[6];
385 assign CCD_DATA[7] = GPIO_1[7];
386 assign CCD_DATA[8] = GPIO_1[8];
387 assign CCD_DATA[9] = GPIO_1[9];
388 assign GPIO_1[11] = CCD_MCLK;
389 assign CCD_FVAL = GPIO_1[13];
390 assign CCD_LVAL = GPIO_1[12];
391 assign CCD_PIXCLK = GPIO_1[10];
392
393 always@(posedge CLOCK_50)
394 CCD_MCLK <= ~CCD_MCLK;
395
396 always@(posedge CCD_PIXCLK) begin
397 rCCD_DATA <= CCD_DATA;
398 rCCD_LVAL <= CCD_LVAL;
399 rCCD_FVAL <= CCD_FVAL;
400 end
401
402 LCM_PLL u0 (
403 .inclk0(CLOCK_27),
404 .c0(CLK_18)
405 );
406
407 LCM_Controller u1 (
408 // Host Side
409 .iRed(Read_DATA2[9:2]),
410 .iGreen({Read_DATA1[14:10],Read_DATA2[14:12]}),
411 .iBlue(Read_DATA1[9:2]),
412 // LCM Side
413 .LCM_DATA(LCM_DATA),
414 .LCM_VSYNC(LCM_VSYNC),
415 .LCM_HSYNC(LCM_HSYNC),
416 .LCM_DCLK(LCM_DCLK),
417 .LCM_SHDB(LCM_SHDB),
418 .LCM_GRST(LCM_GRST),
419 // Control Signals
420 .oDATA_REQ(Read),
421 .iCLK(CLK_18),
422 .iRST_N(DLY_RST_2)
423 );
424
425 Reset_Delay u2 (
426 .iCLK(CLOCK_50),
427 .iRST(KEY[0]),
428 .oRST_0(DLY_RST_0),
429 .oRST_1(DLY_RST_1),
430 .oRST_2(DLY_RST_2)
431 );
432
433 CCD_Capture u3 (
434 .oDATA(mCCD_DATA),
435 .oDVAL(mCCD_DVAL),
436 .oX_Cont(X_Cont),
437 .oY_Cont(Y_Cont),
438 .oFrame_Cont(Frame_Cont),
439 .iDATA(rCCD_DATA),
440 .iFVAL(rCCD_FVAL),
441 .iLVAL(rCCD_LVAL),
442 .iSTART(!KEY[3]),
443 .iEND(!KEY[2]),
444 .iCLK(CCD_PIXCLK),
445 .iRST(DLY_RST_1)
446 );
447
448 RAW2RGB u4 (
449 .oRed(mCCD_R),
450 .oGreen(mCCD_G),
451 .oBlue(mCCD_B),
452 .oDVAL(mCCD_DVAL_d),
453 .iX_Cont(X_Cont),
454 .iY_Cont(Y_Cont),
455 .iDATA(mCCD_DATA),
456 .iDVAL(mCCD_DVAL),
457 .iCLK(CCD_PIXCLK),
458 .iRST(DLY_RST_1)
459 );
460
461 SEG7_LUT_8 u5 (
462 .oSEG0(HEX0),
463 .oSEG1(HEX1),
464 .oSEG2(HEX2),
465 .oSEG3(HEX3),
466 .oSEG4(HEX4),
467 .oSEG5(HEX5),
468 .oSEG6(HEX6),
469 .oSEG7(HEX7),
470 .iDIG(Frame_Cont)
471 );
472
473 Sdram_Control_4Port u6 (
474 // HOST Side
475 .REF_CLK(CLOCK_50),
476 .RESET_N(1'b1),
477 // FIFO Write Side 1
478 .WR1_DATA({sCCD_G[9:5], sCCD_B[9:0]}),
479 .WR1(sCCD_DVAL),
480 .WR1_ADDR(0),
481 .WR1_MAX_ADDR(320*256),
482 .WR1_LENGTH(9'h100),
483 .WR1_LOAD(!DLY_RST_0),
484 .WR1_CLK(CCD_PIXCLK),
485 // FIFO Write Side 2
486 .WR2_DATA( {sCCD_G[4:0], sCCD_R[9:0]}),
487 .WR2(sCCD_DVAL),
488 .WR2_ADDR(22'h100000),
489 .WR2_MAX_ADDR(22'h100000+320*256),
490 .WR2_LENGTH(9'h100),
491 .WR2_LOAD(!DLY_RST_0),
492 .WR2_CLK(CCD_PIXCLK),
493 // FIFO Read Side 1
494 .RD1_DATA(Read_DATA1),
495 .RD1(Read),
496 .RD1_ADDR(320*8),
497 .RD1_MAX_ADDR(320*248),
498 .RD1_LENGTH(9'h100),
499 .RD1_LOAD(!DLY_RST_0),
500 .RD1_CLK(CLK_18),
501 // FIFO Read Side 2
502 .RD2_DATA(Read_DATA2),
503 .RD2(Read),
504 .RD2_ADDR(22'h100000+320*8),
505 .RD2_MAX_ADDR(22'h100000+320*248),
506 .RD2_LENGTH(9'h100),
507 .RD2_LOAD(!DLY_RST_0),
508 .RD2_CLK(CLK_18),
509 // SDRAM Side
510 .SA(DRAM_ADDR),
511 .BA({DRAM_BA_1,DRAM_BA_0}),
512 .CS_N(DRAM_CS_N),
513 .CKE(DRAM_CKE),
514 .RAS_N(DRAM_RAS_N),
515 .CAS_N(DRAM_CAS_N),
516 .WE_N(DRAM_WE_N),
517 .DQ(DRAM_DQ),
518 .DQM({DRAM_UDQM,DRAM_LDQM}),
519 .SDR_CLK(DRAM_CLK)
520 );
521
522 I2C_CCD_Config u7 (
523 // Host Side
524 .iCLK(CLOCK_50),
525 .iRST_N(KEY[1]),
526 .iExposure(SW[15:0]),
527 // I2C Side
528 .I2C_SCLK(GPIO_1[14]),
529 .I2C_SDAT(GPIO_1[15])
530 );
531
532 I2S_LCM_Config u8 (
533 // Host Side
534 .iCLK(CLOCK_50),
535 .iRST_N(KEY[0]),
536 // I2C Side
537 .I2S_SCLK(LCM_SCLK),
538 .I2S_SDAT(LCM_SDAT),
539 .I2S_SCEN(LCM_SCEN)
540 );
541
542 I2C_AV_Config u9 (
543 // Host Side
544 .iCLK(CLOCK_50),
545 .iRST_N(KEY[0]),
546 // I2C Side
547 .I2C_SCLK(I2C_SCLK),
548 .I2C_SDAT(I2C_SDAT)
549 );
550
551 Mirror_Col u10 (
552 // Input Side
553 .iCCD_R(mCCD_R),
554 .iCCD_G(mCCD_G),
555 .iCCD_B(mCCD_B),
556 .iCCD_DVAL(mCCD_DVAL_d),
557 .iCCD_PIXCLK(CCD_PIXCLK),
558 .iRST_N(DLY_RST_1),
559 // Output Side
560 .oCCD_R(sCCD_R),
561 .oCCD_G(sCCD_G),
562 .oCCD_B(sCCD_B),
563 .oCCD_DVAL(sCCD_DVAL)
564 );
565
566 endmodule
Solution
Step 1：
將CCD_SCLK與CCD_FLASH的wire宣告刪除
wire CCD_SCLK;
wire CCD_FLASH;
wire CCD_FLASH;
Step 2：
將GPIO1[15]與GPIO_1[14]的assign刪除
assign GPIO_1[15] = CCD_SDAT;
assign GPIO_1[14] = CCD_SCLK;
assign GPIO_1[14] = CCD_SCLK;
Step 3：
將I2C_CCD_Config的I2C_SCLK與I2C_SDAT直接連到GPIO_1[14]與GPIO_1[15]
I2C_CCD_Config u7 (
// Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[1]),
.iExposure(SW[15:0]),
// I2C Side
.I2C_SCLK(GPIO_1[14]),
.I2C_SDAT(GPIO_1[15])
);
// Host Side
.iCLK(CLOCK_50),
.iRST_N(KEY[1]),
.iExposure(SW[15:0]),
// I2C Side
.I2C_SCLK(GPIO_1[14]),
.I2C_SDAT(GPIO_1[15])
);
完整程式碼下載
DE2_LCM_CCD_inverse.7z
Conclusion
或許你會覺得很瞎，為什麼少了wire就正確了?這個問題我問過友晶的工程師，他們說這應該是Quartus II合成的問題，就Verilog而言並沒有錯。
See Also
(原創) 如何解決DE2範例DE2_CCD_detect左右相反的問題? (IC Design) (DE2) (Quartus II)
(原創) 如何在DE2將CCD影像顯示在彩色LCD上? (純硬體篇) (IC Design) (DE2)
