(筆記) 如何設計一個簡單的ALU電路? (SOC) (Verilog) (MegaCore)

Abstract
以always與case多工器設計一個簡單的ALU電路。

Introduction
使用環境：Quartus II 7.2 SP3 + ModelSim-Altera 6.1g + DE2(Cyclone II EP2C35F672C6)

Method 1：
使用Verilog

alu.v / Verilog

 /* 
 (C) OOMusou 2008 http://oomusou.cnblogs.com
 
 Filename    : alu.v
 Compiler    : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g
 Description : Demo how to write simple ALU
 Release     : 07/12/2008 1.0
 */
 module alu (
   input [2:0] a,
   input [2:0] b,
   input [2:0] sel,
   output reg [7:0] y
 );
 
 always@(a or b or sel) begin
   case(sel)
     3'b000: y = a + b;
     3'b001: y = a - b;
     3'b010: y = a * b;
     3'b011: begin
       y[7:4] = a / b;
       y[3:0] = a % b;
     end
     3'b100: y = a & b;
     3'b101: y = a | b;
     3'b110: y = ~a;
     3'b111: y = a ^ b;
   endcase
 end
 
 endmodule

Method 2：
使用Megafunction

alu_mf.v / Verilog

 /* 
 (C) OOMusou 2008 http://oomusou.cnblogs.com
 
 Filename    : alu_mf.v
 Compiler    : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g
 Description : Demo how to write simple ALU
 Release     : 07/12/2008 1.0
 */
 module alu_mf (
   input  [2:0] a,
   input  [2:0] b,
   input  [2:0] sel,
   output [7:0] y
 );
 
 wire [2:0] add_sum;
 wire add_cout;
 wire [7:0] add = {{4'h0}, add_cout, add_sum};
 wire [7:0] sub;
 wire [7:0] mul;
 wire [3:0] quotient;
 wire [3:0] remain;
 wire [7:0] w_and;
 wire [7:0] w_or;
 wire [7:0] inv;
 wire [7:0] w_xor;
 wire [63:0] w_mux = {w_xor, inv, w_or, w_and, {quotient, remain}, mul, sub, add};
 
 lpm_add_sub # (.lpm_width(3),.lpm_direction("add"))
 u0 (
   .dataa(a),
   .datab(b),
   .result(add_sum),
   .cout(add_cout)
 );
 
 lpm_add_sub # (.lpm_width(3),.lpm_direction("sub"))
 u1 (
   .dataa(a),
   .datab(b),
   .result(sub)
 );
 
 lpm_mult # (.lpm_widtha(3),.lpm_widthb(3),.lpm_widthp(8))
 u2 (
   .dataa(a),
   .datab(b),
   .result(mul)
 );
 
 lpm_divide # (.lpm_widthn(3),.lpm_widthd(3))
 u3 (
   .numer(a),
   .denom(b),
   .quotient(quotient),
   .remain(remain)
 );
 
 lpm_inv # (.lpm_width(8))
 u4 (
   .data(a),
   .result(inv)
 );
 
 lpm_mux # (.lpm_width(8), .lpm_widths(3), .lpm_size(8))
 u5 (
   .data(w_mux),
   .sel(sel),
   .result(y)
 );
 
 assign w_and = and_2(a,b);
 assign w_or  = or_2(a, b);
 assign w_xor = xor_2(a, b);
 
 function [7:0] and_2(input [2:0] a, input [2:0] b);
   and_2 = a & b;
 endfunction
 
 function [7:0] or_2(input [2:0] a, input [2:0] b);
   or_2 = a | b;
 endfunction
 
 function [7:0] xor_2(input [2:0] a, input [2:0] b);
   xor_2 = a ^ b;
 endfunction
 
 endmodule

testbench
alu_tb.v / Verilog

 /* 
 (C) OOMusou 2008 http://oomusou.cnblogs.com
 
 Filename    : alu_tb.v
 Compiler    : Quartus II 7.2 SP3 + ModelSim-Altera 6.1g
 Description : Demo how to write simple ALU testbench
 Release     : 07/12/2008 1.0
 */
 `timescale 1ns/10ps
 module alu_tb;
 reg [2:0] a;
 reg [2:0] b;
 reg [2:0] sel;
 wire [7:0] y;
 
 alu u0 (
   .a(a),
   .b(b),
   .sel(sel),
   .y(y)
 );
 
 initial begin
   a = 3'b111;
   b = 3'b010;
   sel = 3'b000;
 end
 
 always #50 sel = sel + 1;
 
 endmodule

執行結果

pins.tcl

 cmp add_assignment "alu" "" "a[2]"      "LOCATION" "PIN_AD13"
 cmp add_assignment "alu" "" "a[1]"      "LOCATION" "PIN_AF14"
 cmp add_assignment "alu" "" "a[0]"      "LOCATION" "PIN_AE14"
 cmp add_assignment "alu" "" "b[2]"      "LOCATION" "PIN_P25"
 cmp add_assignment "alu" "" "b[1]"      "LOCATION" "PIN_N26"
 cmp add_assignment "alu" "" "b[0]"      "LOCATION" "PIN_N25"
 cmp add_assignment "alu" "" "y[7]"      "LOCATION" "PIN_AC21"
 cmp add_assignment "alu" "" "y[6]"      "LOCATION" "PIN_AD21"
 cmp add_assignment "alu" "" "y[5]"      "LOCATION" "PIN_AD23"
 cmp add_assignment "alu" "" "y[4]"      "LOCATION" "PIN_AD22"
 cmp add_assignment "alu" "" "y[3]"      "LOCATION" "PIN_AC22"
 cmp add_assignment "alu" "" "y[2]"      "LOCATION" "PIN_AB21"
 cmp add_assignment "alu" "" "y[1]"      "LOCATION" "PIN_AF23"
 cmp add_assignment "alu" "" "y[0]"      "LOCATION" "PIN_AE23"
 cmp add_assignment "alu" "" "sel[2]"    "LOCATION" "PIN_V2"

Reference
陸自強 2007，數位系統實習 Quartus II，儒林圖書公司