ULK --- Chap 4: Interrupt Descriptor Table

A system table called Interrupt Descriptor Table (IDT) associates each interrupt or exception vector with

the address of the corresponding interrupt or exception handler. The IDT must be properly initialized before

the kernel enables interrupts.

The IDT format is similar to that of the GDT and LDTs examined in Chapter 2. Each entry corresponds to an

interrupt or an exception vector and consists of an 8-byte descriptor. Thus, a maximum of 256 * 8 = 2048

bytes are required to store the IDT.

The idtr CPU register allows the IDT to be located anywhere in the memory: it specifies both the IDT base 

linear address and its limit (maximum length). It must be initialized before enabling interrupts by using the

lidt assembly language instruction.

The IDT may include three types of descriptors; Figure 4-2 (TextBook) illustrates the meaning of the 64 bits

included in each of them. In particular, the value of the Type field encoded in the bits 40-43 identifies the

descriptor type.

The descriptors are:

Task Gate: Include the TSS selector of the process that must replace the current one when an interrupt signal

occurs.

Interrupt Gate: Includes the Segment Selector and the offset inside the segment of an interrupt or exception

handler. While tansferring control to the proper segment, the processor clears the IF flag, thus disabling further

maksable interrupts.

Trap Gate: Similar to an interrupt gate, except that while transferring control to proper segment, the processor

does not modify the IF flag.

　　　　　　　　　　　　　　Hardware Handling of Interrupts and Exceptions

We now describe how the CPU control unit handles interrupts and exceptions. We assume that the kernel has been

initialized, and thus the CPU is operating in Protected Mode.

After executing an instruction, the cs and eip pair of registers contain the logical address of the next instruction to

be executed. Before dealing with that instruction, the control unit checks whether an interrupt or an exception occurred

while the control unit executes the previous instruction. If one occurred, the control unit does the following:

1. Determines the vector i (0 <= i <= 255) associated with the interrupt or the exception.

2. Reads the ith entry of the IDT referred by the idtr register (we assume in the following description that the entry

contains an interrupt or a trap gate).

3. Gets the base address of the GDT from the gdtr register and looks in the GDT to read the Segment Descriptor

identified by the selector in the IDT entry. This descriptor specifies the base address of the segment that includes

the interrupt or exception handler.

4. Makes sure the interrupt was issued by an authorized source. First, it compares the Current Privilege Level (CPL),

which is stored in the two least significant bits of the cs register, with the Descriptor Privilege Level (DPL) of the

Segement Descriptor included in the GDT. Raises a "General Protection" exception if the CPL is lower than the DPL,

because the interrupt handler cannot have a lower privilege than the program that caused the interrupt. For 

programmed exceptions, makes a further security chcek: compares the CPL with the DPL of the gate descriptor

included in the IDT and raises a "General Exception" exception if the DPL is lower then CPL. This last check makes

it possible to prevent access by user applications to specific trap or interrupt gates.

5. Checks whether a change of privilege level is taking place --- that is, if CPL is different from the selected 

Segment Descriptor's DPL. If so, the control unit must start using the stack that is associated with the new

privilege level. It does this by performing the following steps:

a. Reads the tr register to access the TSS segment of the running process.

b.