Verilog MIPS32 CPU(四)-- RAM

 

 

module ram(
        input clk,
        input wena,
        input [8:0] addr,
        input [31:0] data_in,
        output [31:0] data_out
        );
    
    reg [31:0] state [0:512];
    always@(posedge clk) begin
        if(wena) begin
            if(addr!=0) state[addr]<=data_in;
        end
    end 

    assign data_out=state[addr];
endmodule

 

posted @ 2017-10-01 09:51  liutianchen  阅读(2423)  评论(0编辑  收藏  举报