VGA IP核的制作
今天看了本《系统晶片设计-使用NIOS》这本书,看到VGA IP核的设计不错,特移植到Cyclone III上来,试验一下效果。
顶层代码:binary_VGA.v
1 module binary_VGA ( iDATA, oDATA, iADDR,iWR, 2 iRD, iCS, iRST_N, iCLK, 3 VGA_R, VGA_G, VGA_B, 4 VGA_HS, VGA_VS, VGA_SYNC, 5 VGA_BLANK, VGA_CLK ); 6 7 output [31:0] oDATA; 8 input [31:0] iDATA; 9 input [18:0] iADDR; 10 input iWR,iRD,iCS; 11 input iCLK,iRST_N; 12 13 output [9:0] VGA_R; 14 output [9:0] VGA_G; 15 output [9:0] VGA_B; 16 output VGA_HS; 17 output VGA_VS; 18 output VGA_SYNC; 19 output VGA_BLANK; 20 output VGA_CLK; 21 22 wire iCLK_25; 23 reg [2:0] RGB_EN; 24 reg [31:0] oDATA; 25 wire [18:0] mVGA_ADDR; 26 reg [9:0] oRed; 27 reg [9:0] oGreen; 28 reg [9:0] oBlue; 29 parameter RAM_SIZE = 19'h4B000; 30 31 always@(posedge iCLK or negedge iRST_N) 32 begin 33 if(!iRST_N) 34 begin 35 RGB_EN <= 0; 36 oDATA <= 0; 37 end 38 else 39 begin 40 if(iCS) 41 begin 42 if(iWR) 43 begin 44 case(iADDR) 45 RAM_SIZE+0 : RGB_EN <= iDATA[2:0]; 46 endcase 47 end 48 else if(iRD) 49 begin 50 case(iADDR) 51 RAM_SIZE+0 : oDATA <= RGB_EN ; 52 endcase 53 end 54 end 55 end 56 end 57 58 59 60 ram_binary_VGA u1 ( // Write In Side 61 .data(iDATA[2:0]), 62 .wren(iWR && (iADDR < RAM_SIZE) && iCS), 63 .wraddress({iADDR[18:3],~iADDR[2:0]}), 64 .wrclock(iCLK), 65 // Read Out Side 66 .rdaddress(mVGA_ADDR[18:3]), 67 .rdclock(VGA_CLK), 68 .q(ROM_DATA)); 69 70 71 tff t0(.clk(iCLK),.t(1'b1),.q(iCLK_25)); 72 73 reg [2:0] ADDR_d; 74 reg [2:0] ADDR_dd; 75 wire [7:0] ROM_DATA; 76 77 78 always@(posedge VGA_CLK or negedge iRST_N) 79 begin 80 if(!iRST_N) 81 begin 82 oRed <= 0; 83 oGreen <= 0; 84 oBlue <= 0; 85 ADDR_d <= 0; 86 ADDR_dd <= 0; 87 end 88 else 89 begin 90 ADDR_d <= mVGA_ADDR[2:0]; 91 ADDR_dd <= ~ADDR_d; 92 oRed <= ROM_DATA[ADDR_dd]? 10'b1111111111:10'b00000000; 93 oGreen <= ROM_DATA[ADDR_dd]? 10'b1111111111:10'b00000000; 94 oBlue <= ROM_DATA[ADDR_dd]? 10'b1111111111:10'b00000000; 95 end 96 end 97 98 99 VGA_ctr u0 ( // Host Side 100 .i_RGB_EN(RGB_EN), 101 .oAddress(mVGA_ADDR), 102 .iRed (oRed), 103 .iGreen (oGreen), 104 .iBlue (oBlue), 105 // VGA Side 106 .oVGA_R(VGA_R), 107 .oVGA_G(VGA_G), 108 .oVGA_B(VGA_B), 109 .oVGA_H_SYNC(VGA_HS), 110 .oVGA_V_SYNC(VGA_VS), 111 .oVGA_SYNC(VGA_SYNC), 112 .oVGA_BLANK(VGA_BLANK), 113 .oVGA_CLOCK(VGA_CLK), 114 // Control Signal 115 .iCLK_25(iCLK_25), 116 .iRST_N(iRST_N) ); 117 118 endmodule
VGA_ctl.v 如下:
1 module VGA_ctr(i_RGB_EN,iRed,iGreen,iBlue, 2 oVGA_R,oVGA_G,oVGA_B,oVGA_H_SYNC, 3 oVGA_V_SYNC,oVGA_SYNC,oVGA_BLANK,oVGA_CLOCK, 4 iCLK_25, iRST_N, oAddress); 5 6 7 input iCLK_25; 8 input iRST_N; 9 input [2:0] i_RGB_EN; 10 input [9:0] iRed,iGreen,iBlue; 11 12 output [19:0] oAddress; 13 14 output [9:0] oVGA_R,oVGA_G,oVGA_B; 15 output oVGA_H_SYNC,oVGA_V_SYNC; 16 output oVGA_SYNC; 17 output oVGA_BLANK; 18 output oVGA_CLOCK; 19 20 // H_Sync Generator, Ref. 25 MHz Clock 21 parameter H_SYNC_CYC = 96; 22 parameter H_SYNC_TOTAL= 800; 23 24 reg [9:0] H_Cont; 25 reg oVGA_H_SYNC; 26 always@(posedge iCLK_25 or negedge iRST_N) 27 begin 28 if(!iRST_N) 29 begin 30 H_Cont <= 0; 31 oVGA_H_SYNC <= 0; 32 end 33 else 34 begin 35 // H_Sync Counter 36 if( H_Cont < H_SYNC_TOTAL) //H_SYNC_TOTAL=800 37 H_Cont <= H_Cont+1; 38 else 39 H_Cont <= 0; 40 // H_Sync Generator 41 if( H_Cont < H_SYNC_CYC ) //H_SYNC_CYC =96 42 oVGA_H_SYNC <= 0; 43 else 44 oVGA_H_SYNC <= 1; 45 end 46 end 47 48 parameter V_SYNC_TOTAL= 525; 49 parameter V_SYNC_CYC = 2; 50 reg [9:0] V_Cont; 51 reg oVGA_V_SYNC; 52 53 // V_Sync Generator, Ref. H_Sync 54 always@(posedge iCLK_25 or negedge iRST_N) 55 begin 56 if(!iRST_N) 57 begin 58 V_Cont <= 0; 59 oVGA_V_SYNC <= 0; 60 end 61 else 62 begin 63 // When H_Sync Re-start 64 if(H_Cont==0) 65 begin 66 // V_Sync Counter 67 if( V_Cont < V_SYNC_TOTAL ) //V_SYNC_TOTAL =525 68 V_Cont <= V_Cont+1; 69 else 70 V_Cont <= 0; 71 // V_Sync Generator 72 if( V_Cont < V_SYNC_CYC ) // V_SYNC_CYC =2 73 oVGA_V_SYNC <= 0; 74 else 75 oVGA_V_SYNC <= 1; 76 end 77 end 78 end 79 80 81 parameter H_SYNC_BACK = 45+3; 82 parameter V_SYNC_BACK = 30+2; 83 parameter X_START = H_SYNC_CYC+H_SYNC_BACK+4; 84 parameter Y_START = V_SYNC_CYC+V_SYNC_BACK; 85 parameter H_SYNC_ACT = 640; 86 parameter V_SYNC_ACT = 480; 87 reg [9:0] oVGA_R,oVGA_G,oVGA_B; 88 always@(H_Cont or V_Cont or i_RGB_EN or iRed or 89 iGreen or iBlue ) 90 begin 91 if(H_Cont>=X_START+9 && H_Cont<X_START+H_SYNC_ACT+9 && 92 V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT) 93 begin 94 if (i_RGB_EN[2]==1) 95 oVGA_R=iRed ; 96 else 97 oVGA_R=0; 98 if (i_RGB_EN[1]==1) 99 oVGA_G=iGreen ; 100 else 101 oVGA_G=0; 102 if (i_RGB_EN[0]==1) 103 oVGA_B=iBlue ; 104 else 105 oVGA_B=0; 106 end 107 else 108 begin 109 oVGA_R=0;oVGA_G=0;oVGA_B=0; 110 end 111 end 112 113 114 115 assign oVGA_BLANK = oVGA_H_SYNC & oVGA_V_SYNC; 116 assign oVGA_SYNC = 1'b0; 117 assign oVGA_CLOCK = ~iCLK_25; 118 119 120 121 reg [9:0] oCoord_X,oCoord_Y; 122 reg [19:0] oAddress; 123 always@(posedge iCLK_25 or negedge iRST_N) 124 begin 125 if(!iRST_N) 126 begin 127 oCoord_X <= 0; 128 oCoord_Y <= 0; 129 oAddress <= 0; 130 end 131 else 132 begin 133 if( H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT && 134 V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT ) 135 begin 136 oCoord_X <= H_Cont-X_START; 137 oCoord_Y <= V_Cont-Y_START; 138 oAddress <= oCoord_Y*H_SYNC_ACT+oCoord_X-3; 139 end 140 end 141 end 142 143 endmodule 144 145 146 147 // VGA Side 148 149 // Internal Registers and Wires
ram_binary_VGA的调用见下图:
关于VGA_init.mif的调用,
接下来选择View-Address Radix 选择Decimal;选择View-Memory Radix 选择Binary;选择视窗Edit--Custom Fill Cells,出现如下框图:
完后,添加IP核,
添加入进去IP核即可。注意:SOPC可以自动寻找IP核目录,只限于工程文件夹的子目录,如果在子目录中再添加目录,不可以寻找,必须在sopc中指定相应的目录。
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posted on 2013-06-23 14:37 hunningtu 阅读(1115) 评论(0) 编辑 收藏 举报