反应时间测试电路
在DE2-70开发板上实现的一个反应时间测试电路：
（1）按iKEY[0]键可以复位测试电路；
（2）复位后过一段时间，红灯oLEDG[0]打开，4位BCD计数器开始以毫秒为单位计数。从复位到红灯亮之间的时间可以用iSW[7]~iSW[0]以秒为单位进行设置。
（3）被测试人看到红灯亮时，马上按iKEY[3]键，iKEY[3]键按下后，红灯熄灭，4位计数器停止计数并将此时的计数值显示在数码管上，此计数值即为反映时间。
使用verilog HDL输入，代码如下：
View Code
1 module response_time_test(iCLK_50,iKEY,iSW,oLEDG0,oHEX0,oHEX1,oHEX2,oHEX3);
2 input iCLK_50;
3 input [1:0] iKEY;
4 input [7:0] iSW;
5 output reg oLEDG0;
6 output [0:6] oHEX0,oHEX1,oHEX2,oHEX3;
7
8 reg [25:0] count_1sec;
9 reg [15:0] count_1msec;
10 reg reset_en;
11 reg [7:0] ready_time;
12 reg action_en;
13 reg [3:0] reaction_time[0:3];
14
15 always @ (posedge iCLK_50) begin
16 //to produce 1sec and 1msec
17 count_1sec <= count_1sec + 1'b1;
18 count_1msec <= count_1msec + 1'b1;
19 if(count_1sec == 26'd50000000)//1sec
20 count_1sec <= 26'b0;
21 if(count_1msec == 16'd50000)//1msec
22 count_1msec <= 16'b0;
23
24 if(iKEY[0] == 0)
25 begin
26 reset_en <= 1'b1;//reset enable
27 count_1sec <= 26'b0;
28 ready_time <= 8'b0;
29 oLEDG0 <= 1'b0;
30 action_en <= 1'b0;//action disable
31 reaction_time[0] <= 4'hf;
32 reaction_time[1] <= 4'hf;
33 reaction_time[2] <= 4'hf;
34 reaction_time[3] <= 4'hf;
35 end//end iKEY[0] == 0;
36 else if(reset_en == 1'b1)
37 begin
38 if(count_1sec == 0)
39 begin
40 ready_time <= ready_time + 1'b1;
41 if(ready_time == iSW)
42 begin
43 oLEDG0 <= 1'b1;
44 reset_en <= 1'b0;
45 count_1msec <= 16'b0;
46 action_en <= 1'b1;
47 reaction_time[0] <= 4'h0;
48 reaction_time[1] <= 4'h0;
49 reaction_time[2] <= 4'h0;
50 reaction_time[3] <= 4'h0;
51 end
52 end
53 end//end reset_en == 1'b1;
54 else if(action_en == 1'b1)
55 begin
56 if(count_1msec == 0)
57 begin
58 if(reaction_time[0] == 4'h9)
59 begin
60 reaction_time[0] <= 4'h0;
61 if(reaction_time[1] == 4'h9)
62 begin
63 reaction_time[1] <= 4'h0;
64 if(reaction_time[2] == 4'h9)
65 begin
66 reaction_time[2] <= 4'h0;
67 if(reaction_time[3] == 4'h9)
68 begin
69 reaction_time[3] <= 4'h0;
70 end
71 else
72 reaction_time[3] <= reaction_time[3] + 1'b1;
73 end//end reaction_time[2] == 4'h9
74 else
75 reaction_time[2] <= reaction_time[2] + 1'b1;
76 end//end reaction_time[1] == 4'h9
77 else
78 reaction_time[1] <= reaction_time[1] + 1'b1;
79 end//end reaction_time[0] == 4'h9;
80 else
81 reaction_time[0] <= reaction_time[0] + 1'b1;
82 end//end count_1msec == 0
83 if(iKEY[1] == 1'b0)
84 begin
85 reset_en <= 1'b0;
86 action_en <= 1'b0;
87 oLEDG0 <= 1'b0;
88 end
89 end//end action_en == 1'b1
90 end//end always
91
92 bcd7seg digit0(reaction_time[0],oHEX0);
93 bcd7seg digit1(reaction_time[1],oHEX1);
94 bcd7seg digit2(reaction_time[2],oHEX2);
95 bcd7seg digit3(reaction_time[3],oHEX3);
96 endmodule
97
98 module bcd7seg(bcd,display);
99 input [3:0] bcd;
100 output [0:6] display;
101 reg [0:6] display;
102
103 always @ (bcd)
104 case (bcd)
105 4'h0 : display = 7'b0000001;
106 4'h1 : display = 7'b1001111;
107 4'h2 : display = 7'b0010010;
108 4'h3 : display = 7'b0000110;
109 4'h4 : display = 7'b1001100;
110 4'h5 : display = 7'b0100100;
111 4'h6 : display = 7'b1100000;
112 4'h7 : display = 7'b0001111;
113 4'h8 : display = 7'b0000000;
114 4'h9 : display = 7'b0001100;
115 default : display = 7'b1111111;
116 endcase
117 endmodule
