二段式fsm
1.推荐在敏感表下的默认状态为X,这样描述的好处有2个:
好处1:仿真易观察bug。
好处2:综合对不定态X的处理是"Don't Care",即任何没有定义的状态寄存器向量都会被忽略。
2.对于每个output,一般用combination描述,用task/endtask将output封装起来。
1 //2-paragraph method to describe FSM 2 //Describe sequential state transition in 1 sequential always block 3 //State transition conditions in the other combinational always block 4 //Package state output by task. Then register the output 5 //Westor Wang, Dec. 2006 6 //Verilog Training -- How to write FSM better 7 8 9 module state2 ( 10 input nrst, 11 input clk, 12 input i1, 13 input i2, 14 output reg o1, 15 output reg o2, 16 output reg err 17 ); 18 19 reg [2:0] NS,CS; 20 21 parameter [2:0] //one hot with zero idle 22 IDLE = 3'b000, 23 S1 = 3'b001, 24 S2 = 3'b010, 25 ERROR = 3'b100; 26 27 //first paragraph:sequential state transition 28 always @ (posedge clk or negedge nrst) 29 if (!nrst) 30 CS <= IDLE; 31 else 32 CS <=NS; 33 34 //second paragraph:combinational condition judgment 35 always @ (nrst or CS or i1 or i2) 36 begin 37 NS = 3'bx; //default state x 38 ERROR_out; 39 case (CS) 40 IDLE: begin 41 IDLE_out; 42 if (~i1) NS = IDLE; 43 if (i1 && i2) NS = S1; 44 if (i1 && ~i2) NS = ERROR; 45 end 46 S1: begin 47 S1_out; 48 if (~i2) NS = S1; 49 if (i2 && i1) NS = S2; 50 if (i2 && (~i1)) NS = ERROR; 51 end 52 S2: begin 53 S2_out; 54 if (i2) NS = S2; 55 if (~i2 && i1) NS = IDLE; 56 if (~i2 && (~i1)) NS = ERROR; 57 end 58 ERROR: begin 59 ERROR_out; 60 if (i1) NS = ERROR; 61 if (~i1) NS = IDLE; 62 end 63 endcase 64 end 65 66 67 //package output with task 68 task IDLE_out; 69 {o1,o2,err} = 3'b000; 70 endtask 71 72 task S1_out; 73 {o1,o2,err} = 3'b100; 74 endtask 75 76 task S2_out; 77 {o1,o2,err} = 3'b010; 78 endtask 79 80 task ERROR_out; 81 {o1,o2,err} = 3'b111; 82 endtask 83 84 endmodule
注意:并不是有reg就是时序逻辑,触发器。针对FSM的output组合逻辑。
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