FIFO 深度初探

先一个例子为引:

We have a FIFO which clocks data in at 100MHZ and clocks data out at 80MHz. On the input there is only 80 data in any order during each 100 ciocks. In other words, a 100 input clock will carry only 80 data and the other 20 clocks carry no data(data is scatted in any order). How big the FIFO needs to be to avoid data over/under-run?

Revolution: 假设写入时为最坏情况(背靠背),即在160×(1/100)微秒内写入160个数据,而在这段时间内只能读出160×(1/100)×80个数据,二者之差160-160×(1/100)×80=32

因此该FIFO深度为32. (关键词: 背靠背

以上是个写快读慢的情况(应该用较多的情况)

接着下来是一篇英文fifo文章(感谢翻译者),以此加深理解,

introduction  
One of the most common questions in interviews is how to calculate the depth of a FIFO.
在而试过程中,经常被问及的问题之一就是如何计算一个FIFO的深度。
Fifo is used as buffering element or queueing element in the system, which is by common sense is required only when you slow at reading than the write operation.
FIFO在统中用来作缓冲或者队列,通常情况下,当读速率比写速率慢的时候,需要采用FIFO。
So size of the FIFO basically implies the amount of data required to buffer, which depends upon data rate at which data is written and the data rate at which data is read.
所以FIFO的深度取决于需要缓冲的数据量,缓冲的数据量取决于写速率和读速率
Statistically, Data rate varies in the system majorily depending upon the load in the system. So to obtain safer FIFO size we need to consider the worst case scenario for the data transfer across the FIFO under consideration.
统计表明,系统中数据率的变化主要依赖于系统的负载。所以,为了得到安全的FIFO,在设计时,我们需要考虑最坏情形下的通过FIFO进行的数据传输。
For worst case scenario, Difference between the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered.
最坏情况下,读写数据间的速率差,应该为最大值。也就是说,写操作速率应该取最大的写速率,而读操作应该取选小的读速率。
So in the question itself, data rate of read operation is specified by the number of idle cycles and for write operation, maximum data rate should be considered with no idle cycle.
如问题本身,读操作的数据速率是由空闲周期决定的,而对于写操作,最大的写数据率,应该不考虑空闲周期。
So for write operation, we need to know Data rate = Number of data * rate of clock. Writing side is the source and reading side becomes sink, data rate of reading side depends upon the writing side data rate and its own reading rate which is Frd/Idle_cycle_rd.
因而,对于读操作,我们有 Data rate = Number of data * rate of clock。写方是数据流入的方,而读方是数据露出方。读方的速率取决于写方的速率和自身的读速率(Frd/Idle_cycle_rd.)
In order to know the data rate of write operation, we need to know Number of data in a Burst which we have assumed to be B.
为了获知写方数据速率,我们需要知道在突发模式下的数据量,我们假设其为B.
So following up with the equation as explained below:
Fifo size = Size to be buffered = B - B * Frd / (Fwr* Idle_cycle _rd ).
个人认为应该是B - B * Frd / (Fwr*( Idle_cycle _rd+1) )
参考如下的等式:Fifo size = Size to be buffered = B - B * Frd / (Fwr* Idle_cycle _rd ).
Here we have not considered the sychnronizing latency if Write and Read clocks are Asynchronous. Greater the Synchronizing latency, higher the FIFO size requirement to buffer more additional data written.
这里,我们没有考虑由于异步读写需要同步,所引入的延时。越大的延时,需要越大的FIFO来缓冲更多和写数据。
Example : FIFO Depth Calculation  
        例子:计算FIFO深度
Assume that we have to design a FIFO with following requirements and We want to calculate minumum FIFO depth,
假充我们需要设计如下需求的FIFO,我们需要计算它的最小深度。
 A synchronized fifo 异就FIFO
Writing clock 30MHz - F1    写时钟
Reading clock 40MHz - F2     读时钟
Writing Burst Size - B     突发数据量 
Case 1 : There is 1 idle clock cycle for reading side - I  读方一个空闲周期 
Case 2 : There is 10 idle clock cycle for reading side - I  读方10个空闲周期 
FIFO depth calculation = B - B *(F2/I)/F1  
If if we have alternate read cycles i.e between two read cycle there is IDLE cycle.
如果我们已经改变了读周期,比如,两个读周期中有一个空闲周期。
FIFO depth calculation = B - B * F2/(F1*2)
In our present problem FIFO depth = B - B *40/(30*2)
= B(1-2/3)= B/3
That means if our Burst amount of data is 10 , FIFODEPTH = 10/3 = 3.333 = 4 (approximatly)
 If B = 20 FIFO depth = 20/3 = 6.6 = 7or 8 (clocks are asynchronous)
 If B = 30 FIFO depth = 30/3 = 10   10+1 = 11 (clocks are asynchronous)
If 10 IDLE cycles betweeen two read cycles .
FIFO DEPTH = B - B *F2/(F1*10) .= B(1-4/30)= B * 26 /30
以下较深,需要嚼嚼:(关键词 :链路利用率, 带宽,无解

FIFO的输入输出带宽应该相等,否则进来的永远比出去的多,FIFO总是处于不断积累数据的状态。例如,若写时钟WCLK=200MHZ,读时钟 RCLK=100MHZ,链路利用率均为80%,则呼入FIFO的有效带宽是160W bps(W为数据宽度),呼出的有效带宽为80W bps,则矛盾。此时应该提高读时钟的频率,使FIFO的两端带宽匹配,在此前提下才能计算出有解的FIFO深度。

如果令WCLK = RCLK = 100MHz,则同上例;WCLK = RCLK = 200MHz时亦为32。

如果令WCLK = 200MHz,改为100个WCLK里写入40个,RCLK = 100MHz,10个RCLK里读出8个,则FIFO深度为 80-80×(1/200)×100×(8/10)  = 48

一般化:

写时钟频率: WCLK;

读时钟频率: RCLK;

写时每B个时钟周期内会有A个数据写入FIFO;

读时每Y个时钟周期内会有X个数据读出FIFO;

则FIFO的最小深度是多少?

首先,在一定时间内,写入的数据量应该等于读出的数据量,即必要条件为WCLK×(A/B)= RCLK×(X/Y);

其次,算出写数据的最大burst_length。考虑最坏情况,比如条件会给出每100个写时钟写入80个数据,那么在背靠背的情况下,burst_length = 2×80 = 160;

则:

          FIFO_depth = burst_length -burst_length*(X/Y)*(RCLK/WCLK),

其中的burst_length包含了A和B的信息。

上式可变形为:

         FIFO_depth = burst_length - (burst_length/WCLK)*(RCLK*(X/Y)). 

其中(burst_length/WCLK)表示这个burst的持续时间,(RCLK*(X/Y))表示读的实际速度,两者的乘积自然就是这段时 间读出的数据量,显然burst_length表示这段时间写入的数据量,两者之差为FIFO中残留的数据,这个也就是理论上的FIFO的最小深度。

实际应用中往往是以半空半满信号来指示FIFO的空满状态的,所以实际设计FIFO的时候会至少留出一个数据空间的深度裕量。

posted on 2011-07-05 20:32  蓝色之耀  阅读(859)  评论(0编辑  收藏  举报

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