基于TFT LCD320*240 液晶显示 —— 碰碰球

首先看看ET0350G0DM6 3.5英寸液晶的时序图（DE MODE）：

采用DE MODE，硬件上一定要把HSYNC和VSYNC两个引脚悬空。

液晶最高频率为10MHz，我们可以用PLL分频至20MHz送该液晶驱动模块，驱动代码（SystemVerilog）如下：

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module DE (
            input clk,
            input reset,
   output reg[5:0] red,
   output reg[5:0] green,
   output reg[5:0] blue,
   output reg  DCLK,
   output ENB,
   output LEDCTRL);

assign LEDCTRL = 0;

always@(posedge clk or negedge reset)
begin
 if(!reset) DCLK <= 1'd0;
 else       DCLK <= ~DCLK;
end

reg[8:0] cnt_h;

always@(negedge DCLK or negedge reset)
begin
if(!reset)               cnt_h <= 9'd0;
else if(cnt_h < 9'd380)  cnt_h ++;
else                  cnt_h <= 9'd0;
end

wire ENB_h;

assign ENB_h = (cnt_h < 9'd320)?1'b1:1'b0;

reg[8:0] cnt_v;

always@(negedge ENB_h or negedge reset)
begin
if(!reset)               cnt_v <= 9'd0;
else if(cnt_v < 9'd250)  cnt_v ++;
else                     cnt_v <= 9'd0;
end

wire ENB_v = (cnt_v < 9'd243)?1'b1:1'b0;

assign ENB = ENB_v && ENB_h;

reg[8:0] x;

reg flag;

always@(posedge ENB_v or negedge reset)
begin
      if(! reset) begin x <= 9'd30;flag <= 1'b0;end
      else if(!flag)
         begin
            x++;
           if(x==9'd290) flag <= 1'b1;
         end
      else
        begin
           x--;
           if(x==9'd30) flag <= 1'b0;
        end
end

reg[8:0] y;
reg flag1;

always@(posedge ENB_v or negedge reset)
begin
      if(! reset) begin y <= 9'd30;flag1 <= 1'b0;end
      else if(!flag1)
         begin
            y++;
           if(y==9'd210) flag1 <= 1'b1;
         end
      else
        begin
           y--;
           if(y==9'd30) flag1 <= 1'b0;
        end
end

always@(*)
begin
   if((cnt_h-x)**2 + (cnt_v-y)**2 < 18'd900 )
         begin  red<=6'b11_1111; green<=6'b00_0000; blue<=6'b00_0000;end
   else  begin  red<=6'b00_0000; green<=6'b00_0000; blue<=6'b00_0000;end
end

endmodule

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