重学Verilog(3)——参数化模块
1.parameter方法
首先有这样一个模块
1 module half_adder(co,sum,a,b); 2 output co,sum; 3 input a,b; 4 parameter and_delay = 2; 5 parameter xor_delay = 4; 6 and #and_delay u1(co,a,b); 7 xor #xor_delay u2(sum,a,b); 8 endmodule
1.1 defparam方法(Altera)
1 module top (...); 2 input....; 3 output....; 4 defparam u_halfadder.and_dealy = 10,u_halfadder.xor_dealy = 10;
5 half_adder u_halfadder(...);
6 endmodule
1.2 例化时代入(Xilinx)
module top (...); input....; output....; half_adder ＃( 10 , 20) u_halfadder (...); endmodule
2.include方法
M95XXX_Parameters.v 参数定义文件
ref.https://www.cnblogs.com/undermyownmoon/p/7628731.html
`define MEM_ADDR_BITS 11 //memory address bits `define PAGE_ADDR_BITS 6 //page address bits
M95xxx_Driver.v 驱动文件
`include "M95XXX_Parameters.v" reg[`MEM_ADDR_BITS-1:0] memory_address; reg[`PAGE_ADDR_BITS-1:0] page_address;
