1.2选1多路选择器
1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 ENTITY mux21 IS 4 PORT ( a,b : IN STD_LOGIC; 5 s : IN STD_LOGIC; 6 y : OUT STD_LOGIC ); 7 END ENTITY mux21; 8 9 ARCHITECTURE one OF mux21 IS 10 BEGIN 11 y <= a WHEN s = '0' ELSE 12 b WHEN s = '1'; 13 END ARCHITECTURE one;
2.锁存器
1 library IEEE; 2 use IEEE.STD_LOGIC_1164.ALL; 3 4 entity latch is 5 Port ( d : in STD_LOGIC; 6 ena : in STD_LOGIC; 7 q : out STD_LOGIC 8 ); 9 end entity latch; 10 11 architecture one of latch is 12 signal sig_save : STD_LOGIC; 13 begin 14 process (d,ena) 15 begin 16 17 if ena = '1' then 18 sig_save <= d; 19 end if ; 20 21 q <= sig_save ; 22 end process ; 23 end architecture one;
3.全加器
1 --或门逻辑描述 2 library IEEE; 3 use IEEE.STD_LOGIC_1164.ALL; 4 5 ENTITY or2 IS 6 PORT (a,b :IN STD_LOGIC; c : OUT STD_LOGIC ); 7 END ENTITY or2; 8 ARCHITECTURE fu1 OF or2 IS 9 BEGIN 10 c <= a OR b ; 11 END ARCHITECTURE fu1; 12 13 --半加器描述 14 LIBRARY IEEE; 15 USE IEEE.STD_LOGIC_1164.ALL; 16 17 ENTITY h_adder IS 18 PORT (a,b : IN STD_LOGIC; co,so : OUT STD_LOGIC); 19 END ENTITY h_adder; 20 ARCHITECTURE fh1 OF h_adder IS 21 BEGIN 22 so <= (a OR b)AND(a NAND b);--与非的作用：实现1+1=0 23 co <= NOT( a NAND b);--与非：只有在1 NAND 1时返回0，其他情况返回1 24 END ARCHITECTURE fh1; 25 26 --全加器顶层设计描述 27 28 LIBRARY IEEE; 29 USE IEEE.STD_LOGIC_1164.ALL; 30 31 ENTITY f_adder IS 32 PORT ( ain,bin,cin : IN STD_LOGIC; 33 cout,sum : OUT STD_LOGIC ); 34 END ENTITY f_adder; 35 36 ARCHITECTURE fd1 OF f_adder IS 37 COMPONENT h_adder 38 PORT ( a,b : IN STD_LOGIC; 39 co,so : OUT STD_LOGIC); 40 END COMPONENT; 41 COMPONENT or2 42 PORT (a,b : IN STD_LOGIC; 43 c : OUT STD_LOGIC); 44 END COMPONENT; 45 SIGNAL d,e,f : STD_LOGIC; 46 BEGIN 47 u1 : h_adder PORT MAP( a =>ain,b =>bin,co=>d,so =>e); 48 u2 : h_adder PORT MAP( a =>e,b =>cin,co =>f,so =>sum); 49 u3 : or2 PORT MAP(a =>d,b =>f,c =>cout); 50 END ARCHITECTURE fd1 ;
