串口收 程序FPGA
module detect_module
(
CLK,RSTn,
RX_Pin_In,
H2L_Sig
);
input CLK;
input RSTn;
input RX_Pin_In;
output H2L_Sig;
reg H2L_F1;
reg H2L_F2;
always@(posedge CLK or negedge RSTn)
if(!RSTn) //有无复位
begin
H2L_F1<=1'b1;
H2L_F2<=1'b1; //非阻塞语句
end
else
begin
H2L_F1<=RX_Pin_In;
H2L_F2<=H2L_F1;
end
assign H2L_Sig=H2L_F2&!H2L_F1; //有低时,H to L 输出高电平
endmodule
module rx_bps_module
(
CLK,RSTn,
Count_Sig,
BPS_CLK
);
input CLK;
input RSTn;
input Count_Sig;
output BPS_CLK;
reg[12:0]Count_BPS;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
Count_BPS<=13'd0;
else if(Count_BPS==12'd5207) //9600 bps 传输速度使一位数据的周期是 0.000104166666666667s 。
Count_BPS<=13'd0; //以50Mhz时钟频率要得到上述的定时需要: N = 0.000104166666666667 / ( 1 / 50Mhz ) = 5208
else if(Count_Sig)
Count_BPS<=Count_BPS+1'b1;
else
Count_BPS<=13'd0;
assign BPS_CLK=(Count_BPS==13'd2604)? 1'b1 : 1'b0; //采集数据要求“在周期的中间”,那么结果是 5208 / 2 ,BPS_CLK为采样时钟
endmodule
module rx_control_module
(
CLK,RSTn,
H2L_Sig,RX_Pin_In,BPS_CLK,RX_En_Sig,
Count_Sig,RX_Data,RX_Done_Sig
);
input CLK;
input RSTn;
input H2L_Sig;
input RX_En_Sig;
input RX_Pin_In;
input BPS_CLK;
output Count_Sig;
output [7:0]RX_Data;
output RX_Done_Sig;
reg [3:0] i;
reg [7:0] rData;
reg isCount;
reg isDone;
always@(posedge CLK or negedge RSTn)
if(!RSTn)
begin
i<=4'd0;
rData<=8'd0;
isCount<=1'b0;
isDone<=1'b0;
end
else if(RX_En_Sig)
case(i)
4'd0:
if(H2L_Sig) begin i<=i+1'b1; isCount<=1'b1;end
4'd1:
if(BPS_CLK) begin i<=i+1'b1;end
4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9:
if(BPS_CLK) begin i<=i+1'b1;rData[i-2]<=RX_Pin_In;end
4'd10:
if(BPS_CLK) begin i<=i+1'b1;end
4'd11:
if(BPS_CLK) begin i<=i+1'b1;end
4'd12:
begin i<=i+1'b1;isDone<=1'b1;isCount<=1'b0;end
4'd13:
begin i<=1'b0;isDone<=1'b0;end
endcase
assign Count_Sig=isCount;
assign RX_Data=rData;
assign RX_Done_Sig=isDone;
endmodule
module rx_module
(
CLK,RSTn,
RX_Pin_In,RX_En_Sig,
RX_Done_Sig,RX_Data
);
input CLK;
input RSTn;
input RX_Pin_In;
input RX_En_Sig;
output [7:0]RX_Data;
output RX_Done_Sig;
wire H2L_Sig;
detect_module U1
(
.CLK(CLK),
.RSTn(RSTn),
.RX_Pin_In(RX_Pin_In), //input from top
.H2L_Sig(H2L_Sig) //output to U3
);
wire BPS_CLK;
rx_bps_module U2
(
.CLK(CLK),
.RSTn(RSTn),
.Count_Sig(Count_Sig), //input from U3
.BPS_CLK(BPS_CLK) // output to U3
);
wire Count_Sig;
rx_control_module U3
(
.CLK(CLK),
.RSTn(RSTn),
.H2L_Sig(H2L_Sig), //input from U1
.RX_En_Sig(RX_En_Sig), //input from top
.RX_Pin_In(RX_Pin_In), //input from top
.BPS_CLK(BPS_CLK), //input from U2
.Count_Sig(Count_Sig), //output to U2
.RX_Data(RX_Data), //output to top
.RX_Done_Sig(RX_Done_Sig) //output to top
);
endmodule